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IS24C32B-2PLI PDF预览

IS24C32B-2PLI

更新时间: 2024-09-20 04:10:39
品牌 Logo 应用领域
美国芯成 - ISSI 存储内存集成电路光电二极管双倍数据速率可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
页数 文件大小 规格书
17页 133K
描述
64K-bit/32K-bit 2-WIRE SERIAL CMOS EEPROM

IS24C32B-2PLI 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP8,.3
针数:8Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.76最大时钟频率 (fCLK):1 MHz
数据保留时间-最小值:100耐久性:1000000 Write/Erase Cycles
I2C控制字节:1010DDDRJESD-30 代码:R-PDIP-T8
JESD-609代码:e3长度:9.325 mm
内存密度:32768 bit内存集成电路类型:EEPROM
内存宽度:8功能数量:1
端子数量:8字数:4096 words
字数代码:4000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:4KX8封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP8,.3
封装形状:RECTANGULAR封装形式:IN-LINE
并行/串行:SERIAL峰值回流温度(摄氏度):260
电源:2/5 V认证状态:Not Qualified
座面最大高度:4.57 mm串行总线类型:I2C
最大待机电流:0.000001 A子类别:EEPROMs
最大压摆率:0.003 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.8 V标称供电电压 (Vsup):2.5 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:7.62 mm最长写入周期时间 (tWC):5 ms
写保护:HARDWAREBase Number Matches:1

IS24C32B-2PLI 数据手册

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®
IS24C32A/B  
IS24C64A/B  
ISSI  
64K-bit/32K-bit  
2-WIRE SERIAL CMOS EEPROM  
APRIL2006  
FEATURES  
DESCRIPTION  
• Two-Wire Serial Interface, I2CTM Compatible  
–Bi-directional data transfer protocol  
• Wide Voltage Operation  
The IS24C32A/B and IS24C64A/B are electrically  
erasable PROM devices that use the standard 2-  
wire interface for communications. The IS24C32A/B  
and IS24C64A/B contain a memory array of 32K-  
bits (4K x 8) and 64K-bits (8K x 8), respectively.  
Each device is organized into 32 byte pages for  
page write mode.  
–Vcc = 1.8V to 5.5V  
• 400 KHz (2.5V) and 1MHz (5.0V) Compatible  
• Low Power CMOS Technology  
–Standby Current less than 6 µA (5.0V)  
–Read Current less than 2 mA (5.0V)  
–Write Current less than 3 mA (5.0V)  
• Hardware Data Protection  
This EEPROM operates in a wide voltage range of  
1.8V to 5.5V to be compatible with most application  
voltages. ISSI designed this device family to be a  
practical, low-power 2-wire EEPROM solution.  
The devices are available in 8-pin PDIP, 8-pin  
SOIC, 8-pin TSSOP, and 8-pin MSOP packages.  
–IS24C32A/64A: WP protects entire array  
–IS24C32B/64B: WP protects top quarter of  
array  
• Sequential Read Feature  
The IS24C32A/32B/64A/64B (IS24CXX) maintains  
compatibility with the popular 2-wire bus protocol,  
so it is easy to use in applications implementing  
this bus type. The simple bus consists of the  
Serial Clock wire (SCL) and the Serial Data wire  
(SDA). Using the bus, a Master device such as a  
microcontroller is usually connected to one or  
more Slave devices such as this device. The bit  
stream over the SDA line includes a series of  
bytes, which identifies a particular Slave device,  
an instruction, an address within that Slave device,  
and a series of data, if appropriate. The IS24CXX  
has a Write Protect pin (WP) to allow blocking of  
any write instruction transmitted over the bus.  
• Filtered Inputs for Noise Suppression  
• Self time write cycle with auto clear  
5 ms max.@ 2.5V  
• Organization:  
–IS24C32A/B: 4Kx8 (128 pages of 32 bytes)  
–IS24C64A/B: 8Kx8 (256 pages of 32 bytes)  
• 32 Byte Page Write Buffer  
• High Reliability  
–Endurance: 1,000,000 Cycles  
–Data Retention: 100 Years  
• Automotive and Industrial temperature ranges  
• 8-pin PDIP, 8-pin SOIC, 8-pin TSSOP, and 8-pin  
MSOP packages  
• Lead-free Available  
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
1
Rev. A  
04/12/06  

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