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IS24C128A-2PLI

更新时间： 2024-11-08 04:58:35
品牌 Logo 应用领域
美国芯成 - ISSI 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
17页 125K
描述
128K-bit/ 256K-bit 2-WIRE SERIAL CMOS EEPROM

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中文翻译

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IS24C128A-2PLI 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：DIP包装说明：DIP, DIP8,.3
针数：8Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.32.00.51
风险等级：5.56最大时钟频率 (fCLK)：1 MHz
数据保留时间-最小值：40耐久性：100000 Write/Erase Cycles
I2C控制字节：1010DDDRJESD-30 代码：R-PDIP-T8
JESD-609代码：e3长度：9.325 mm
内存密度：131072 bit内存集成电路类型：EEPROM
内存宽度：8湿度敏感等级：3
功能数量：1端子数量：8
字数：16384 words字数代码：16000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：16KX8
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP8,.3封装形状：RECTANGULAR
封装形式：IN-LINE并行/串行：SERIAL
峰值回流温度（摄氏度）：250电源：2/5 V
认证状态：Not Qualified座面最大高度：4.57 mm
串行总线类型：I2C最大待机电流：0.000015 A
子类别：EEPROMs最大压摆率：0.003 mA
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：1.8 V
标称供电电压 (Vsup)：2.5 V表面贴装：NO
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn) - annealed端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：10宽度：7.62 mm
最长写入周期时间 (tWC)：5 ms写保护：HARDWARE

IS24C128A-2PLI 数据手册

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®
IS24C128A  
IS24C256A  
128K-bit/ 256K-bit  
ISSI  
ADVANCEDINFORMATION  
JULY2006  
2-WIRE SERIAL CMOS EEPROM  
FEATURES  
DESCRIPTION  
• Two-Wire Serial Interface, I2CTM compatible  
–Bi-directional data transfer protocol  
• Wide Voltage Operation  
The IS24C128A/256A is an electrically erasable PROM  
device that uses the standard 2-wire interface for  
communications. The IS24C128A is 128K-bit (16Kx8)  
and the IS24C256A is 256K-bit (32Kx8). These  
EEPROM are offered in a wide operating voltage range  
of 1.8V to 5.5V to be compatible with most application  
voltages. ISSI designed the IS24C128A/256A to be an  
efficient 2-wire EEPROM solution. The devices are  
packaged in 8-pin PDIP, 8-pin (JEDEC) SOIC, and 8-  
pin (EIAJ) SOIC.  
–Vcc = 1.8V to 5.5V  
• 400 KHz (2.5V) and 1 MHz (5.0V) compatibility  
• Low Power CMOS Technology  
–Active Current less than 3 mA (2.5V)  
–Standby Current less than 20 µA (2.5V)  
• Hardware Data Protection  
–Write Protect Pin  
The IS24C128A/256A maintains compatibility with the  
popular 2-wire bus protocol, so it is easy to design into  
applications implementing this bus type. The simple  
bus consists of the Serial Clock wire (SCL) and the  
Serial Data wire (SDA). Using the bus, a Master device  
such as a microcontroller is usually connected to one  
or more Slave devices such as the IS24C128A/256A.  
The bit stream over the SDA line includes a series of  
bytes, which identifies a particular Slave device, an  
instruction, an address within that Slave device, and a  
series of data, if appropriate. The IS24C128A/256A has  
a Write Protect pin (WP) to allow blocking of any write  
instruction transmitted over the bus.  
• Sequential Read Feature  
• Filtered Inputs for Noise Suppression  
• Self time write cycle with auto clear  
–5 ms @ 2.5V  
• Organization:  
–16Kx8 (256 pages of 64 bytes)  
–32Kx8 (512 pages of 64 bytes)  
• 64 Byte Page Write Buffer  
• High Reliability  
–Endurance: 1,000,000 Cycles  
–Data Retention: 40 Years  
• Industrial and Automotive temperature ranges  
• 8-pin PDIP, 8-pin (JEDEC) SOIC, and 8-pin  
(EIAJ) SOIC packages  
• Lead-free available  
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability  
arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany  
publishedinformationandbeforeplacingordersforproducts.  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
1
ADVANCEDINFORMATION Rev. 00B  
06/27/06  
1234567...17

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