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IS24C128-3GLA3 PDF预览

IS24C128-3GLA3

更新时间: 2024-09-20 05:39:31
品牌 Logo 应用领域
美国芯成 - ISSI 存储内存集成电路光电二极管双倍数据速率可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
页数 文件大小 规格书
16页 247K
描述
128K-bit 2-WIRE SERIAL CMOS EEPROM

IS24C128-3GLA3 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP8,.25
针数:8Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.25最大时钟频率 (fCLK):1 MHz
数据保留时间-最小值:40耐久性:100000 Write/Erase Cycles
I2C控制字节:10100DDRJESD-30 代码:R-PDSO-G8
JESD-609代码:e3长度:4.9 mm
内存密度:131072 bit内存集成电路类型:EEPROM
内存宽度:8湿度敏感等级:3
功能数量:1端子数量:8
字数:16384 words字数代码:16000
工作模式:SYNCHRONOUS最高工作温度:125 °C
最低工作温度:-40 °C组织:16KX8
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:SERIAL
峰值回流温度(摄氏度):260电源:3/5 V
认证状态:Not Qualified座面最大高度:1.73 mm
串行总线类型:I2C最大待机电流:0.000002 A
子类别:EEPROMs最大压摆率:0.003 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:3.9 mm
最长写入周期时间 (tWC):5 ms写保护:HARDWARE
Base Number Matches:1

IS24C128-3GLA3 数据手册

 浏览型号IS24C128-3GLA3的Datasheet PDF文件第2页浏览型号IS24C128-3GLA3的Datasheet PDF文件第3页浏览型号IS24C128-3GLA3的Datasheet PDF文件第4页浏览型号IS24C128-3GLA3的Datasheet PDF文件第5页浏览型号IS24C128-3GLA3的Datasheet PDF文件第6页浏览型号IS24C128-3GLA3的Datasheet PDF文件第7页 
IS24C128  
128K-bit 2-WIRE SERIAL  
CMOS EEPROM  
MAY2007  
FEATURES  
DESCRIPTION  
The IS24C128 is an electrically erasable PROM device  
that uses the standard 2-wire interface for  
• Organization:  
– 16K-bit x 8-bit  
communications. The IS24C128 contains a memory  
array of 128K-bits (16,384 x 8), and is further  
subdivided into 256 pages of 64 bytes each for page-  
write mode. This EEPROM is offered in operating  
voltages of 2.5V to 5.5V (IS24C128-3) to be compatible  
with most application voltages. ISSI designed the  
IS24C128 to be a low-cost and low-power 2-wire  
EEPROM solution. The devices are packaged in 8-pin  
PDIP and 8-pin SOIC.  
• 64-Byte Page Write Buffer  
• Two-Wire Serial Interface  
– Bi-directional data transfer protocol  
• Low Power CMOS Technology  
– Active Current less than 2 mA (5V)  
– Standby Current less than 5 µA (5V)  
– Standby Current less than 2 µA (2.5V)  
• Low Voltage Operation  
The IS24C128 maintains compatibility with the popular  
2-wire bus protocol, so it is easy to design into  
applications implementing this bus type. The simple  
bus consists of the Serial Clock wire (SCL) and the  
Serial Data wire (SDA). Using the bus, a Master  
device such as a microcontroller is usually connected  
to one or more Slave devices such as the IS24C128.  
The bit stream over the SDA line includes a series of  
bytes, which identifies a particular Slave device, an  
instruction, an address within that Slave device, and a  
series of data, if appropriate. The IS24C128 has a  
Write Protect pin (WP) to allow blocking of any write  
instruction transmitted over the bus.  
– IS24C128-3: Vcc = 2.5V to 5.5V  
• 400 KHz (I2C Protocol) Compatibility  
• Hardware Data Protection  
– Write Protect pin  
• Sequential Read Feature  
• Filtered Inputs for Noise Suppression  
• Self time Write cycle with auto clear  
– 5 ms @ 2.5V  
• High Reliability  
– Endurance: 100,000 Cycles  
– Data Retention: 40 Years  
• Industrial and Automotive temperature ranges  
• 8-pin PDIP and 8-pin SOIC  
• Lead-free available  
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability  
arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany  
publishedinformationandbeforeplacingordersforproducts.  
Integrated Silicon Solution, Inc. — www.issi.com  
1
Rev. C  
05/08/07  

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