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IRS21084PBF PDF预览

IRS21084PBF

更新时间: 2024-11-18 03:44:31
品牌 Logo 应用领域
英飞凌 - INFINEON 外围驱动器驱动程序和接口接口集成电路光电二极管
页数 文件大小 规格书
25页 554K
描述
HALF-BRIDGE DRIVER

IRS21084PBF 技术参数

是否Rohs认证:符合生命周期:Active
包装说明:ROHS COMPLIANT, PLASTIC, MS-001AC, DIP-14Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:1.2Is Samacsys:N
内置保护:TRANSIENT; UNDER VOLTAGE接口集成电路类型:HALF BRIDGE BASED PERIPHERAL DRIVER
JESD-30 代码:R-PDIP-T14长度:19.305 mm
功能数量:1端子数量:14
最高工作温度:125 °C最低工作温度:-40 °C
输出电流流向:SOURCE AND SINK封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:15 V
认证状态:Not Qualified座面最大高度:5.33 mm
子类别:MOSFET Drivers最大供电电压:20 V
最小供电电压:10 V标称供电电压:15 V
表面贴装:NO技术:CMOS
温度等级:AUTOMOTIVE端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED断开时间:0.28 µs
接通时间:0.3 µs宽度:7.62 mm
Base Number Matches:1

IRS21084PBF 数据手册

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Data Sheet No. PD60260  
/
IRS2108 IRS21084(S)PbF  
HALF-BRIDGE DRIVER  
Packages  
Features  
Floating channel designed for bootstrap operation  
Fully operational to +600 V  
Tolerant to negative transient voltage, dV/dt  
8-Lead PDIP  
immune  
Gate drive supply range from 10 V to 20 V  
Undervoltage lockout for both channels  
14-Lead PDIP  
3.3 V, 5 V, and 15 V input logic compatible  
Cross-conduction prevention logic  
Matched propagation delay for both channels  
High-side output in phase with HIN input  
Low-side output out of phase with  
input  
ꢆꢈꢉ  
Logic and power ground +/- 5 V offset  
Internal 540 ns deadtime, and programmable up  
to 5 µs with one external R resistor (IRS21084)  
8-Lead SOIC  
14-Lead SOIC  
DT  
Lower di/dt gate driver for better noise immunity  
RoHS compliant  
Description  
Feature Comparison  
The IRS2108/IRS21084 are high volt-  
age, high speed power MOSFET and  
ꢁꢗꢎꢝꢝꢞ  
ꢜꢎꢘ!ꢊꢜꢍꢛꢎꢘ  
ꢋꢗꢟꢠꢟꢘꢍꢛꢎꢘ  
ꢙꢎꢚꢛꢜ  
ꢈꢘꢋꢊꢍ  
ꢙꢎꢚꢛꢜ  
ꢓꢟꢖ!ꢍꢛꢡꢟ  
%ꢘꢝ&  
t
/t  
on off  
%ꢘꢝ&  
ꢕꢖꢗꢍ  
'ꢗꢎꢊꢘ!ꢌꢕꢛꢘꢝ  
IGBT drivers with dependent high- and  
low-side referenced output channels.  
Proprietary HVIC and latch immune  
CMOS technologies enable ruggedized  
monolithic construction. The logic input  
is compatible with standard CMOS or  
LSTTL output, down to 3.3 V logic. The  
output drivers feature a high pulse cur-  
9:ꢐꢏ*9;ꢐ:  
9:ꢐꢏ<  
ꢁꢅꢇ  
ꢃꢃ*ꢁꢅꢇ  
ꢁꢅꢇ  
ꢄꢈꢉ*ꢆꢈꢉ  
ꢄꢈꢉ*ꢆꢈꢉ  
ꢘꢎ  
ꢘꢎꢘꢟ  
99ꢐ*9ꢐꢐ  
99ꢐ*9ꢐꢐ  
9:ꢐ=  
ꢈꢘꢍꢟꢗꢘꢖꢙꢌ><ꢐ  
ꢕꢗꢎꢚꢗꢖꢡꢡꢖ@ꢙꢟꢌ><ꢐꢌꢞꢌ>ꢐꢐꢐ  
ꢈꢘꢍꢟꢗꢘꢖꢙꢌ><ꢐ  
ꢢꢟꢝ  
9:ꢐ=<  
ꢃꢃ*ꢁꢅꢇ  
ꢁꢅꢇ  
9:ꢐA*9;ꢐ9  
9:ꢐA<  
ꢈꢉ*ꢃꢓ  
ꢢꢟꢝ  
ꢢꢟꢝ  
J>ꢐ*9ꢐꢐ  
:ꢏꢐ*:<ꢐ  
ꢕꢗꢎꢚꢗꢖꢡꢡꢖ@ꢙꢟꢌ><ꢐꢌꢞꢌ>ꢐꢐꢐ  
ꢃꢃ*ꢁꢅꢇ  
ꢄꢈꢉ*ꢆꢈꢉ  
ꢈꢘꢍꢟꢗꢘꢖꢙꢌ:ꢐꢐ  
9;ꢐ<  
ꢁꢅꢇ  
rent buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an  
N-channel power MOSFET or IGBT in the high-side configuration which operates up to 600 V.  
Typical Connection  
ꢊꢋꢌꢍꢎꢌꢏꢐꢐꢌꢀ  
ꢁꢁ  
ꢁꢁ  
ꢄꢈꢉ  
ꢆꢈꢉ  
ꢄꢈꢉ  
ꢆꢈꢉ  
ꢄꢅ  
ꢑꢅ  
ꢆꢅꢒꢓ  
ꢁꢅꢇ  
ꢆꢅ  
ꢊꢋꢌꢍꢎꢌꢏꢐꢐꢌꢀ  
IRS21084  
IRS2108  
ꢄꢅ  
ꢁꢁ  
ꢁꢁ  
ꢄꢈꢉ  
ꢆꢈꢉ  
ꢓꢑ  
ꢄꢈꢉ  
ꢆꢈꢉ  
ꢑꢅ  
ꢆꢅꢒꢓ  
(Refer to Lead Assignments for correct pin  
configuration). These diagrams show  
electrical connections only. Please refer to  
our Application Notes and DesignTips for  
proper circuit board layout.  
ꢁꢅꢇ  
ꢆꢅ  
ꢃꢃ  
ꢃꢃ  
ꢓꢑ  
www.irf.com  
1

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