IRFZ48

更新时间： 2024-09-14 22:51:39

品牌	Logo	应用领域
恩智浦 - NXP		晶体晶体管开关局域网
页数	文件大小	规格书
8页	68K
描述
N-channel enhancement mode TrenchMOS transistor

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中文翻译

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IRFZ48 数据手册

Philips Semiconductors

Product specification

N-channel enhancement mode

TrenchMOS^TMtransistor

IRFZ48N

GENERAL DESCRIPTION

QUICK REFERENCE DATA

N-channel enhancement mode

standard level field-effect power

transistor in a plastic envelope using

’trench’ technology. The device

features very low on-state resistance

and has integral zener diodes giving

ESD protection up to 2kV. It is

intended for use in switched mode

power supplies and general purpose

switching applications.

SYMBOL

PARAMETER

MAX.

UNIT

V_DS

I_D

P_tot

T_j

Drain-source voltage

Drain current (DC)

Total power dissipation

Junction temperature

Drain-source on-state

140

175

˚C

mΩ

R_DS(ON)

resistance

V_GS= 10 V

PINNING - TO220AB

PIN CONFIGURATION

SYMBOL

DESCRIPTION

tab

gate

drain

source

tab drain

1 2 3

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V_DS

V_DGR

±V_GS

I_D

I_DM

Drain-source voltage

Drain-gate voltage

Gate-source voltage

Drain current (DC)

210

140

175

˚C

R_GS= 20 kΩ

T_mb= 25 ˚C

T_mb= 100 ˚C

T_mb= 25 ˚C

Drain current (DC)

Drain current (pulse peak value)

Total power dissipation

Storage & operating temperature

P_tot

T_stg, T_j

- 55

ESD LIMITING VALUE

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V_C

Electrostatic discharge capacitor

voltage, all pins

Human body model

(100 pF, 1.5 kΩ)

THERMAL RESISTANCES

SYMBOL PARAMETER

CONDITIONS

TYP.

MAX.

UNIT

R_{th j-mb}

Thermal resistance junction to

mounting base

1.1

K/W

R_{th j-a}

Thermal resistance junction to

ambient

in free air

K/W

February 1999

Rev 1.000

12 3 4 5 6 7 8

中文翻译

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