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IOP480-AA66BI PDF预览

IOP480-AA66BI

更新时间: 2024-01-09 07:54:05
品牌 Logo 应用领域
PLX 时钟数据传输PC驱动外围集成电路驱动器
页数 文件大小 规格书
11页 111K
描述
PCI Bus Controller, CMOS, PBGA225, 27 X 27 MM, 2.65 MM HEIGHT, PLASTIC, BGA-225

IOP480-AA66BI 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:BGA包装说明:BGA, QFP208,1.2SQ,20
针数:225Reach Compliance Code:unknown
ECCN代码:3A991.A.2HTS代码:8542.31.00.01
风险等级:5.88地址总线宽度:32
位大小:32总线兼容性:PCI; POWERPC
最大时钟频率:33 MHz最大数据传输速率:264 MBps
驱动器接口标准:IEEE 1149.1外部数据总线宽度:32
JESD-30 代码:S-PBGA-B225长度:27 mm
端子数量:225最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:QFP208,1.2SQ,20
封装形状:SQUARE封装形式:GRID ARRAY
电源:3.3 V认证状态:Not Qualified
座面最大高度:2.65 mm速度:66 MHz
子类别:Microprocessors最大压摆率:200 mA
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:BALL端子节距:1.5 mm
端子位置:BOTTOM宽度:27 mm
uPs/uCs/外围集成电路类型:BUS CONTROLLER, PCIBase Number Matches:1

IOP480-AA66BI 数据手册

 浏览型号IOP480-AA66BI的Datasheet PDF文件第2页浏览型号IOP480-AA66BI的Datasheet PDF文件第3页浏览型号IOP480-AA66BI的Datasheet PDF文件第4页浏览型号IOP480-AA66BI的Datasheet PDF文件第5页浏览型号IOP480-AA66BI的Datasheet PDF文件第6页浏览型号IOP480-AA66BI的Datasheet PDF文件第7页 
IOP 480 AA  
Design Note Rev. 1.3  
March 2002  
Design Note Documentation  
A.  
Affected Silicon Revision  
This document details Design Notes for the following silicon:  
Product  
Part Number  
Description  
Status  
60MHz Local Bus  
208-pin PQFP Product  
IOP 480 AA  
IOP480-AA60PI  
In production October 1999  
66MHz Local Bus  
208-pin PQFP Product  
60MHz Local Bus  
225-pin PBGA Product  
66MHz Local Bus  
225-pin PBGA Product  
IOP 480 AA  
IOP 480 AA  
IOP 480 AA  
IOP480-AA66PI  
IOP480-AA60BI  
IOP480-AA66BI  
In production October 1999  
In production October 1999  
In production October 1999  
B.  
Documentation Status  
The following documentation is the baseline functional description of the silicon.  
Errata are defined as behaviors in the affected silicon that do not match  
behaviors detailed in this documentation.  
Document  
IOP 480 Data Book  
Revision  
2.0  
See www.plxtech.com  
for latest revision  
Description  
Released Data Book  
IOP 480 Errata  
Publication Date  
July 2000  
IOP 480 AA Errata  
Documentation  
C.  
Design Note Summary  
#
1
2
3
Description  
End-of-Transfer (EOT) During Chaining DMA End Link Mode with Write-back  
DMA Channel 2 with End-of-Transfer (EOTx#) asserted coincident with ADS#  
Zero Wait State SRAM Writes  
External local master write to IOP 480 internal configuration registers with WAIT# being used  
to insert wait states  
4
5
6
7
8
9
Modifying internal configuration registers that affect on-going transfers  
Operation of IOP 480 Buffers in 3.3 Volt Signaling Environment  
LCSx# Chip Select output delayed when IOP 480 is initiating access to SRAM  
CompactPCI Hot Swap Insertion Bit Status  
DMPAF# (Direct Master Programmable Almost Full) negation timing  
Messaging Unit data corruption if Queue Prefetch (Inbound Free List FIFO Prefetch and/or  
Outbound Post List FIFO Prefetch) is enabled  
10  
11 Local Bus Timeout with SDRAM  
12 WAIT# input signal when using the Memory Controller  
Confidential  
Document number: DN-IOP 480 Rev AA-SIL-1.3  
-1-  

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