ACTS630MS
Radiation Hardened EDAC
(Error Detection and Correction)
January 1996
Features
Pinouts
28 PIN CERAMIC DUAL-IN-LINE, MIL-STD-1835
DESIGNATOR CDIP-T28, LEAD FINISH C
• Devices QML Qualified in Accordance with MIL-PRF-38535
• Detailed Electrical and Screening Requirements are Contained in
SMD# 5962-96721 and Intersil’s QM Plan
TOP VIEW
• 1.25 Micron Radiation Hardened SOS CMOS
DEF
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
1
2
3
4
5
6
7
8
9
28 VCC
27 SEF
26 S1
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
• Single Event Upset (SEU) Immunity: <1 x 10-10 Errors/Bit/Day
(Typ)
25 S0
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm2/mg
• Dose Rate Upset . . . . . . . . . . . . . . . . >1011 RAD (Si)/s, 20ns Pulse
• Dose Rate Survivability. . . . . . . . . . . >1012 RAD (Si)/s, 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55oC to +125oC
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
24 CB0
23 CB1
22 CB2
21 CB3
20
CB4
DB8 10
DB9 11
19 CB5
18 DB15
17 DB14
16 DB13
15 DB12
DB10 12
DB11 13
GND 14
• Input Logic Levels
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current ≤ 1µA at VOL, VOH
• Fast Propagation Delay . . . . . . . . . . . . . . . . 37ns (Max), 24ns (Typ)
28 PIN CERAMIC FLATPACK, MIL-STD-1835
DESIGNATOR CDFP3-F28, LEAD FINISH C
TOP VIEW
Description
The Intersil ACTS630MS is a Radiation Hardened 16-bit parallel error
detection and correction circuit. It uses a modified Hamming code to
generate a 6-bit check word from each 16-bit data word. The check word
is stored with the data word during a memory write cycle; during a
memory read cycle a 22-bit word is taken form memory and checked for
errors. Single bit errors in the data words are flagged and corrected. Sin-
gle bit errors in check words are flagged but not corrected. The position
of the incorrect bit is pinpointed, in both cases, by the 6-bit error
syndrome code which is output during the error correction cycle.
DEF
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
GND
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
SEF
S1
S0
CB0
CB1
CB2
CB3
CB4
CB5
DB15
DB14
DB13
DB12
9
10
11
12
13
14
The ACTS630MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of a radiation hardened,
high-speed, CMOS/SOS Logic Family.
The ACTS630MS is supplied in a 28 lead Ceramic Flatpack (K suffix) or
a 28 Lead Ceramic Dual-In-Line Package (D suffix).
Ordering Information
PART NUMBER
5962F9672101VXC
5962F9672101VYC
ACTS630D/Sample
ACTS630K/Sample
ACTS630HMSR
TEMPERATURE RANGE
SCREENING LEVEL
MIL-PRF-38535 Class V
MIL-PRF-38535 Class V
Sample
PACKAGE
o
o
-55 C to +125 C
28 Lead SBDIP
o
o
-55 C to +125 C
28 Lead Ceramic Flatpack
28 Lead SBDIP
o
25 C
o
25 C
Sample
28 Lead Ceramic Flatpack
Die
o
25 C
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Spec Number 518786
File Number 3204.1
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
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