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5962F9671301VCC PDF预览

5962F9671301VCC

更新时间: 2024-02-17 16:23:41
品牌 Logo 应用领域
英特矽尔 - INTERSIL 触发器逻辑集成电路
页数 文件大小 规格书
3页 110K
描述
Radiation Hardened Dual D Flip Flop with Set and Reset

5962F9671301VCC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DFP包装说明:DFP, FL14,.3
针数:14Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.55
系列:ACTJESD-30 代码:R-CDFP-F14
JESD-609代码:e0负载电容(CL):50 pF
逻辑集成电路类型:D FLIP-FLOP最大I(ol):0.008 A
位数:1功能数量:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C输出极性:COMPLEMENTARY
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:DFP
封装等效代码:FL14,.3封装形状:RECTANGULAR
封装形式:FLATPACK峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 VProp。Delay @ Nom-Sup:20 ns
传播延迟(tpd):20 ns认证状态:Not Qualified
筛选级别:MIL-PRF-38535 Class V座面最大高度:2.92 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:FLAT端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
总剂量:300k Rad(Si) V触发器类型:POSITIVE EDGE
宽度:6.285 mm最小 fmax:79 MHz

5962F9671301VCC 数据手册

 浏览型号5962F9671301VCC的Datasheet PDF文件第2页浏览型号5962F9671301VCC的Datasheet PDF文件第3页 
TM  
ACTS74MS  
Radiation Hardened Dual D  
Flip Flop with Set and Reset  
January 1996  
Features  
Pinouts  
14 PIN CERAMIC DUAL-IN-LINE  
MIL-STD-1835 DESIGNATOR CDIP2-T14,  
LEAD FINISH C  
• Devices QML Qualified in Accordance with MIL-PRFF-38535  
• Detailed Electrical and Screening Requirements are Contained in  
SMD# 5962-96713 and Intersil’s QM Plan  
itle  
CTS  
MS)  
b-  
TOP VIEW  
• 1.25 Micron Radiation Hardened SOS CMOS  
R1  
D1  
1
2
3
4
5
6
7
14 VCC  
13 R2  
12 D2  
11 CP2  
10 S2  
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)  
-10  
t
• Single Event Upset (SEU) Immunity: <1 x 10  
(Typ)  
Errors/Bit/Day  
CP1  
S1  
adia-  
n
rd-  
ed  
al D  
p
p
th  
tand  
set)  
2
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm /mg  
Q1  
11  
• Dose Rate Upset . . . . . . . . . . . . . . . . >10 RAD (Si)/s, 20ns Pulse  
Q1  
9
8
Q2  
Q2  
12  
• Dose Rate Survivability. . . . . . . . . . . >10 RAD (Si)/s, 20ns Pulse  
GND  
• Latch-Up Free Under Any Conditions  
o
o
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55 C to +125 C  
• Significant Power Reduction Compared to ALSTTL Logic  
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V  
14 PIN CERAMIC FLATPACK  
MIL-STD-1835 DESIGNATOR CDFP3-F14,  
LEAD FINISH C  
• Input Logic Levels  
- VIL = 0.8V Max  
TOP VIEW  
1
2
3
4
5
6
7
14  
13  
VCC  
R2  
thor  
R1  
D1  
- VIH = VCC/2 Min  
• Input Current 1µA at VOL, VOH  
D2  
12  
11  
10  
CP1  
S1  
ey-  
rds  
ter-  
CP2  
S2  
• Fast Propagation Delay. . . . . . . . . . . . . . . . 20ns (Max), 13ns (Typ)  
Q1  
Q2  
Q1  
9
8
Description  
Q2  
GND  
The Intersil ACTS74MS is a Radiation Hardened Dual D Flip Flop with  
Set(s) and Reset (R). The logic level at data input is transferred to the  
output during the positive transition of the clock. The Set and Reset are  
independent from the clock and accomplished by a low level on the  
appropriate input.  
mi-  
n-  
ctor,  
dia-  
n
rd-  
ed,  
,
The ACTS74MS utilizes advanced CMOS/SOS technology to achieve  
high-speed operation. This device is a member of a radiation hardened,  
high-speed, CMOS/SOS Logic Family.  
The ACTS74MS is supplied in a 14 lead Ceramic Flatpack (K suffix) or a  
14 Lead Ceramic Dual-In-Line Package (D suffix).  
d
Ordering Information  
rd,  
L,  
tel-  
,
D,  
ass  
PART NUMBER  
5962F9671301VCC  
5962F9671301VXC  
ACTS74D/Sample  
ACTS74K/Sample  
ACTS74HMSR  
TEMPERATURE RANGE  
-55oC to +125oC  
-55oC to +125oC  
25oC  
SCREENING LEVEL  
PACKAGE  
MIL-PRF-38535 Class V  
14 Lead SBDIP  
MIL-PRF-38535 Class V  
14 Lead Ceramic Flatpack  
14 Lead SBDIP  
Sample  
Sample  
Die  
25oC  
14 Lead Ceramic Flatpack  
Die  
25oC  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc.  
Spec Number 518787  
File Number 3382.1  
Copyright © Intersil Americas Inc. 2001, All Rights Reserved  
1

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