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5962F9671101VYC

更新时间： 2024-01-20 02:16:03
品牌 Logo 应用领域
英特矽尔 - INTERSIL 逻辑集成电路
页数 文件大小 规格书
4页 493K
描述
Radiation Hardened EDAC (Error Detection and Correction Circuit)

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5962F9671101VYC 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：DFP
包装说明：DFP, FL28,.4针数：28
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
风险等级：5.68Is Samacsys：N
系列：ACJESD-30 代码：R-CDFP-F28
JESD-609代码：e0逻辑集成电路类型：ERROR DETECTION AND CORRECTION CIRCUIT
位数：16功能数量：1
端子数量：28最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：DFP
封装等效代码：FL28,.4封装形状：RECTANGULAR
封装形式：FLATPACK峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V传播延迟（tpd）：37 ns
认证状态：Not Qualified筛选级别：MIL-PRF-38535 Class V
座面最大高度：2.92 mm子类别：Arithmetic Circuits
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Tin/Lead (Sn/Pb)端子形式：FLAT
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED总剂量：300k Rad(Si) V
宽度：12.445 mmBase Number Matches：1

5962F9671101VYC 数据手册

 浏览型号5962F9671101VYC的Datasheet PDF文件第2页浏览型号5962F9671101VYC的Datasheet PDF文件第3页浏览型号5962F9671101VYC的Datasheet PDF文件第4页 
ACS630MS  
Radiation Hardened EDAC  
(Error Detection and Correction Circuit)  
January 1996  
Features  
Pinouts  
28 PIN CERAMIC DUAL-IN-LINE, MIL-STD-1835  
DESIGNATOR CDIP2-T28, LEAD FINISH C  
TOP VIEW  
• Devices QML Qualified in Accordance with MIL-PRF-38535  
• Detailed Electrical and Screening Requirements are Contained in  
SMD# 5962-96711 and Intersil’ QM Plan  
• 1.25 Micron Radiation Hardened SOS CMOS  
DEF  
DB0  
DB1  
DB2  
DB3  
DB4  
DB5  
DB6  
DB7  
1
2
3
4
5
6
7
8
9
28 VCC  
27 SEF  
26 S1  
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)  
• Single Event Upset (SEU) Immunity: <1 x 10-10 Errors/Bit/Day  
(Typ)  
25 S0  
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm2/mg  
• Dose Rate Upset . . . . . . . . . . . . . . . . >1011 RAD (Si)/s, 20ns Pulse  
• Dose Rate Survivability. . . . . . . . . . . >1012 RAD (Si)/s, 20ns Pulse  
• Latch-Up Free Under Any Conditions  
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55oC to +125oC  
• Significant Power Reduction Compared to ALSTTL Logic  
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V  
24 CB0  
23 CB1  
22 CB2  
21 CB3  
20  
CB4  
DB8 10  
DB9 11  
19 CB5  
18 DB15  
17 DB14  
16 DB13  
15 DB12  
DB10 12  
DB11 13  
GND 14  
• Input Logic Levels  
- VIL = 30% of VCC Max  
- VIH = 70% of VCC Min  
• Input Current ≤ 1µA at VOL, VOH  
• Fast Propagation Delay . . . . . . . . . . . . . . . . 37ns (Max), 24ns (Typ)  
28 PIN CERAMIC FLATPACK, MIL-STD-1835  
DESIGNATOR CDFP3-F28, LEAD FINISH C  
TOP VIEW  
Description  
The Intersil ACS630MS is a Radiation Hardened 16-bit parallel error  
detection and correction circuit. It uses a modified Hamming code to  
generate a 6-bit check word from each 16-bit data word. The check word  
is stored with the data word during a memory write cycle; during a  
memory read cycle a 22-bit word is taken form memory and checked for  
errors. Single bit errors in the data words are flagged and corrected.  
Single bit errors in check words are flagged but not corrected. The  
position of the incorrect bit is pinpointed, in both cases, by the 6-bit error  
syndrome code which is output during the error correction cycle.  
DEF  
DB0  
DB1  
DB2  
DB3  
DB4  
DB5  
DB6  
DB7  
DB8  
DB9  
DB10  
DB11  
GND  
1
2
3
4
5
6
7
8
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
VCC  
SEF  
S1  
S0  
CB0  
CB1  
CB2  
CB3  
CB4  
CB5  
DB15  
DB14  
DB13  
DB12  
9
10  
11  
12  
13  
14  
The ACS630MS utilizes advanced CMOS/SOS technology to achieve  
high-speed operation. This device is a member of a radiation hardened,  
high-speed, CMOS/SOS Logic Family.  
The ACS630MS is supplied in a 28 lead Ceramic Flatpack (K suffix) or a  
28 Lead Ceramic Dual-In-Line Package (D suffix).  
Ordering Information  
PART NUMBER  
5962F9671101VXC  
5962F9671101VYC  
ACS630D/Sample  
ACS630K/Sample  
ACS630HMSR  
TEMPERATURE RANGE  
SCREENING LEVEL  
MIL-PRF-38535 Class V  
MIL-PRF-38535 Class V  
Sample  
PACKAGE  
o
o
-55 C to +125 C  
28 Lead SBDIP  
o
o
-55 C to +125 C  
28 Lead Ceramic Flatpack  
28 Lead SBDIP  
o
25 C  
o
25 C  
Sample  
28 Lead Ceramic Flatpack  
Die  
o
25 C  
Die  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
Spec Number 518781  
File Number 3199.1  
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999  
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