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5962F9670801VCC PDF预览

5962F9670801VCC

更新时间： 2024-01-21 15:44:01
品牌 Logo 应用领域
英特矽尔 - INTERSIL 逻辑集成电路
页数 文件大小 规格书
3页 60K
描述
Radiation Hardened 9-Bit Odd/ Even Parity Generator Checker

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5962F9670801VCC 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DFP包装说明：DFP, FL14,.3
针数：14Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.73
Is Samacsys：N系列：AC
JESD-30 代码：R-CDFP-F14JESD-609代码：e0
逻辑集成电路类型：PARITY GENERATOR/CHECKER位数：9
功能数量：1端子数量：14
最高工作温度：125 °C最低工作温度：-55 °C
输出极性：COMPLEMENTARY封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：DFP封装等效代码：FL14,.3
封装形状：RECTANGULAR封装形式：FLATPACK
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
传播延迟（tpd）：23 ns认证状态：Not Qualified
筛选级别：MIL-PRF-38535 Class V座面最大高度：2.92 mm
子类别：Arithmetic Circuits最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：FLAT端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
总剂量：300k Rad(Si) V宽度：6.285 mm
Base Number Matches：1

5962F9670801VCC 数据手册

 浏览型号5962F9670801VCC的Datasheet PDF文件第2页浏览型号5962F9670801VCC的Datasheet PDF文件第3页 
ACS280MS  
Radiation Hardened 9-Bit Odd/  
Even Parity Generator Checker  
January 1996  
Features  
Pinouts  
14 PIN CERAMIC DUAL-IN-LINE  
MIL-STD-1835 DESIGNATOR, CDIP2-T14,  
LEAD FINISH C  
• Devices QML Qualified in Accordance with MIL-PRF-38535  
• Detailed Electrical and Screening Requirements are Contained in  
SMD# 5962-96708 and Intersil’ QM Plan  
TOP VIEW  
• 1.25 Micron Radiation Hardened SOS CMOS  
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)  
• Single Event Upset (SEU) Immunity: <1 x 10-10 Errors/Bit/Day  
(Typ)  
I6  
I7  
1
2
3
4
5
6
7
14 VCC  
13 I5  
12 I4  
11 I3  
NC  
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm2/mg  
• Dose Rate Upset . . . . . . . . . . . . . . . . >1011 RAD (Si)/s, 20ns Pulse  
• Dose Rate Survivability. . . . . . . . . . . >1012 RAD (Si)/s, 20ns Pulse  
• Latch-Up Free Under Any Conditions  
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55oC to +125oC  
• Significant Power Reduction Compared to ALSTTL Logic  
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V  
I8  
EVEN  
ODD  
GND  
10 I2  
9
8
I1  
I0  
• Input Logic Levels  
- VIL = 30% of VCC Max  
- VIH = 70% of VCC Min  
14 PIN CERAMIC FLATPACK  
MIL-STD-1835 DESIGNATOR, CDFP3-F14  
LEAD FINISH C  
• Input Current ≤ 1µA at VOL, VOH  
TOP VIEW  
• Fast Propagation Delay . . . . . . . . . . . . . . . . 23ns (Max), 15ns (Typ)  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
I6  
I7  
VCC  
I5  
Description  
The Intersil ACS280MS is a Radiation Hardened 9-bit odd/even parity  
generator checker device. Both odd and even parity outputs are available  
for generating or checking parity for words up to 9 bits long. Even parity  
is indicated (EVEN output high) when an even number of data inputs are  
high. Odd parity is indicated (ODD output high) when an odd number of  
data inputs are high. Parity checking for larger words can be accom-  
plished by tying EVEN output to any input of an additional ACS280MS.  
NC  
I4  
I8  
I3  
EVEN  
ODD  
GND  
I2  
I1  
I0  
8
The ACS280MS utilizes advanced CMOS/SOS technology to achieve  
high-speed operation. This device is a member of a radiation hardened,  
high-speed, CMOS/SOS Logic Family.  
The ACS280MS is supplied in a 14 lead Ceramic Flatpack (K suffix) or a  
Ceramic Dual-In-Line Package (D suffix).  
Ordering Information  
PART NUMBER  
5962F9670801VCC  
5962F9670801VXC  
ACS280D/Sample  
ACS280K/Sample  
ACS280HMSR  
TEMPERATURE RANGE  
SCREENING LEVEL  
PACKAGE  
o
o
-55 C to +125 C  
MIL-PRF-38535 Class V  
14 Lead SBDIP  
o
o
-55 C to +125 C  
MIL-PRF-38535 Class V  
14 Lead Ceramic Flatpack  
14 Lead SBDIP  
o
25 C  
Sample  
Sample  
Die  
o
25 C  
14 Lead Ceramic Flatpack  
Die  
o
25 C  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
Spec Number 518819  
File Number 3568.1  
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999  
1
123

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