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5962F9670501VCC PDF预览

5962F9670501VCC

更新时间: 2024-02-10 23:06:08
品牌 Logo 应用领域
英特矽尔 - INTERSIL 逻辑集成电路驱动
页数 文件大小 规格书
4页 54K
描述
Radiation Hardened Quad Buffer, Three-State

5962F9670501VCC 技术参数

生命周期:Transferred包装说明:,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.65系列:AC
JESD-30 代码:R-CDFP-F14JESD-609代码:e4
逻辑集成电路类型:BUS DRIVER位数:1
功能数量:4端口数量:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装形状:RECTANGULAR封装形式:FLATPACK
认证状态:Not Qualified最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:GOLD
端子形式:FLAT端子位置:DUAL
总剂量:300k Rad(Si) VBase Number Matches:1

5962F9670501VCC 数据手册

 浏览型号5962F9670501VCC的Datasheet PDF文件第2页浏览型号5962F9670501VCC的Datasheet PDF文件第3页浏览型号5962F9670501VCC的Datasheet PDF文件第4页 
ACS125MS  
Radiation Hardened  
Quad Buffer, Three-State  
January 1996  
Features  
Pinouts  
14 PIN CERAMIC DUAL-IN-LINE  
MIL-STD-1835 DESIGNATOR, CDIP2-T14,  
LEAD FINISH C  
• Devices QML Qualified in Accordance with MIL-PRF-38535  
• Detailed Electrical and Screening Requirements are Contained in  
SMD# 5962-96705 and Intersil’s QM Plan  
TOP VIEW  
• 1.25 Micron Radiation Hardened SOS CMOS  
OE1  
A1  
1
2
3
4
5
6
7
14 VCC  
13 OE4  
12 A4  
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)  
• Single Event Upset (SEU) Immunity: <1 x 10-10 Errors/Bit/Day  
(Typ)  
Y1  
OE2  
A2  
11 Y4  
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm2/mg  
• Dose Rate Upset . . . . . . . . . . . . . . . . >1011 RAD (Si)/s, 20ns Pulse  
• Dose Rate Survivability. . . . . . . . . . . >1012 RAD (Si)/s, 20ns Pulse  
• Latch-Up Free Under Any Conditions  
10 OE3  
Y2  
9
8
A3  
Y3  
GND  
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55oC to +125oC  
• Significant Power Reduction Compared to ALSTTL Logic  
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V  
14 PIN CERAMIC FLATPACK  
MIL-STD-1835 DESIGNATOR, CDFP3-F14  
LEAD FINISH C  
TOP VIEW  
• Input Logic Levels  
- VIL = 30% of VCC Max  
- VIH = 70% of VCC Min  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
VCC  
OE4  
A4  
OE1  
A1  
Y1  
• Input Current 1µA at VOL, VOH  
Y4  
OE2  
A2  
• Fast Propagation Delay . . . . . . . . . . . . . . . . 15ns (Max), 10ns (Typ)  
OE3  
A3  
Y2  
Description  
Y3  
GND  
8
The Intersil ACS125MS is a Radiation Hardened Quad Buffer with  
Three-State outputs. Each output has it’s own enable input, which when  
“HIGH” puts the output in a high impedance state.  
The ACS125MS utilizes advanced CMOS/SOS technology to achieve  
high-speed operation. This device is a member of radiation hardened,  
high-speed, CMOS/SOS Logic Family.  
The ACS125MS is supplied in a 14 lead Ceramic Flatpack (K suffix) or a  
Ceramic Dual-In-Line Package (D suffix).  
Ordering Information  
PART NUMBER  
5962F9670501VCC  
5962F9670501VXC  
ACS125D/Sample  
ACS125K/Sample  
ACS125HMSR  
TEMPERATURE RANGE  
SCREENING LEVEL  
PACKAGE  
o
o
-55 C to +125 C  
MIL-PRF-38535 Class V  
14 Lead SBDIP  
o
o
-55 C to +125 C  
MIL-PRF-38535 Class V  
14 Lead Ceramic Flatpack  
14 Lead SBDIP  
o
25 C  
Sample  
Sample  
Die  
o
25 C  
14 Lead Ceramic Flatpack  
Die  
o
25 C  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
Spec Number 518817  
File Number 3565.1  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
1

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