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5962F9568902VXC

更新时间： 2024-01-24 09:30:26
品牌 Logo 应用领域
英特矽尔 - INTERSIL 接口集成电路
页数 文件大小 规格书
3页 68K
描述
Radiation Hardened 3.3V Quad Differential Line Receiver

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5962F9568902VXC 技术参数

生命周期：Active包装说明：DFP,
Reach Compliance Code：unknown风险等级：5.72
差分输出：NO输入特性：DIFFERENTIAL SCHMITT TRIGGER
接口集成电路类型：LINE RECEIVER接口标准：EIA-422
JESD-30 代码：R-CDFP-F16功能数量：4
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：DFP封装形状：RECTANGULAR
封装形式：FLATPACK认证状态：Qualified
最大接收延迟：65 ns接收器位数：4
筛选级别：MIL-PRF-38535 Class V最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES温度等级：MILITARY
端子形式：FLAT端子位置：DUAL
总剂量：300k Rad(Si) V

5962F9568902VXC 数据手册

 浏览型号5962F9568902VXC的Datasheet PDF文件第2页浏览型号5962F9568902VXC的Datasheet PDF文件第3页 
HS-26CLV32RH  
TM  
Data Sheet  
August 2000  
File Number 4907  
Radiation Hardened 3.3V Quad Differential  
Line Receiver  
Features  
• Electrically Screened to SMD # 5962-95689  
The Intersil HS-26CLV32RH is a radiation hardened 3.3V  
quad differential line receiver designed for digital data  
transmission over balanced lines, in low voltage, RS-422  
protocol applications. Radiation hardened CMOS processing  
assures low power consumption, high speed, and reliable  
operation in the most severe radiation environments.  
• QML Qualified per MIL-PRF-38535 Requirements  
• 1.2 Micron Radiation Hardened CMOS  
- Total Dose. . . . . . . . . . . . . . . . . . . . . 300 krad(Si)(Max)  
2
- Single Event Upset LET . . . . . . . . . . .100MeV/mg/cm )  
- Single Event Latch-up Immune  
The HS-26CLV32RH has an input sensitivity of 200mV (Typ)  
over a common mode input voltage range of -4V to +7V. The  
receivers are also equipped with input fail safe circuitry,  
which causes the outputs to go to a logic “1” when the inputs  
are open. The device has unique inputs that remain high  
impedance when the receiver is disabled or powered-down,  
maintaining signal integrity in multi-receiver applications.  
• Low Stand-by Current. . . . . . . . . . . . . . . . . . . 13mA(Max)  
• Operating Supply Range . . . . . . . . . . . . . . . . 3.0V to 3.6V  
• Enable Input Levels . . . . V > (.7)(V ); V < (.3)(V  
)
IH  
DD  
IL  
DD  
• CMOS Output Levels . . . . . . . . V  
> 2.55V; V < 0.4V  
OH  
OL  
• Input Fail Safe Circuitry  
• High Impedance Inputs when Disabled or Powered-down  
Specifications for Rad Hard QML devices are controlled  
by the Defense Supply Center in Columbus (DSCC). The  
SMD numbers listed here must be used when ordering.  
o
o
• Full -55 C to 125 C Military Temperature Range  
Pinouts  
Detailed Electrical Specifications for these devices are  
contained in SMD 5962-95689. A “hot-link” is provided  
on our homepage for downloading.  
HS1-26CLV32RH 16 LEAD CERAMIC SIDEBRAZE DIP  
MIL-STD-1835: CDIP2-T16  
TOP VIEW  
www.intersil.com/spacedefense/space.asp  
AIN  
AIN  
1
2
3
4
5
6
7
8
16 V  
DD  
Ordering Information  
15 BIN  
TEMP.  
RANGE  
AOUT  
ENABLE  
COUT  
CIN  
14 BIN  
13 BOUT  
12 ENABLE  
11 DOUT  
10 DIN  
o
ORDERING NO.  
5962F9568902QEC  
5962F9568902QXC  
5962F9568902V9A  
5962F9568902VEC  
5962F9568902VXC  
INTERNAL MKT. NO.  
HS1-26CLV32RH-8  
HS9-26CLV32RH-8  
HS0-26CLV32RH-Q  
HS1-26CLV32RH-Q  
HS9-26CLV32RH-Q  
( C)  
-55 to 125  
-55 to 125  
25  
CIN  
9
DIN  
GND  
-55 to 125  
-55 to 125  
HS9-26CLV32RH 16 LEAD FLATPACK  
MIL-STD-1835: CDFP4-F16  
TOP VIEW  
HS1-26CLV32RH/PROTO HS1-26CLV32RH/PROTO -55 to 125  
HS9-26CLV32RH/PROTO HS9-26CLV32RH/PROTO -55 to 125  
AIN  
AIN  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
V
DD  
Logic Diagram  
BIN  
AOUT  
ENABLE  
COUT  
CIN  
BIN  
ENABLE ENABLE DIN DIN  
CIN CIN  
BIN BIN  
AIN AIN  
BOUT  
ENABLE  
DOUT  
DIN  
+
-
+
-
+
-
+
-
CIN  
GND  
DIN  
DOUT  
COUT  
BOUT  
AOUT  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000  
1
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