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4030B PDF预览

4030B

更新时间: 2024-01-14 23:35:55
品牌 Logo 应用领域
英特矽尔 - INTERSIL
页数 文件大小 规格书
7页 62K
描述
CMOS Quad Exclusive-OR Gate

4030B 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete包装说明:DIP, DIP14,.3
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.92JESD-30 代码:R-XDIP-T14
JESD-609代码:e0逻辑集成电路类型:XOR GATE
湿度敏感等级:2A端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:CERAMIC封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):250
电源:3/15 V施密特触发器:NO
子类别:Gates表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30

4030B 数据手册

 浏览型号4030B的Datasheet PDF文件第2页浏览型号4030B的Datasheet PDF文件第3页浏览型号4030B的Datasheet PDF文件第4页浏览型号4030B的Datasheet PDF文件第5页浏览型号4030B的Datasheet PDF文件第6页浏览型号4030B的Datasheet PDF文件第7页 
CD4030BMS  
CMOS Quad Exclusive-OR Gate  
December 1992  
Features  
Pinout  
CD4030BMS  
TOP VIEW  
• High Voltage Type (20V Rating)  
• Medium-Speed Operation  
- tPHL, tPLH = 65ns (typ) at VDD = 10V, CL = 50pF  
A
B
1
2
3
4
5
6
7
14 VDD  
• 100% Tested for Quiescent Current at 20V  
• Standardized Symmetrical Output Characteristics  
• 5V, 10V and 15V Parametric Ratings  
13  
12  
H
G
J = A  
K = C  
B
• Maximum Input Current Of 1µA at 18V Over Full  
Package-Temperature Range;  
- 100nA at 18V and +25oC  
D
11 M = G  
10 L = E  
H
C
F
D
9
8
F
E
• Noise Margin (Over Full Package Temperature Range):  
- 1V at VDD = 5V  
VSS  
- 2V at VDD = 10V  
- 2.5V at VDD = 15V  
• Meets All Requirements of JEDEC Tentative Standard  
No. 13B, “Standard Specifications for Description of  
‘B’ Series CMOS Devices”  
Functional Diagram  
Applications  
1
A
3
4
J
2
B
• Even and Odd-Parity Generators and Checkers  
• Logical Comparators  
5
6
C
K
L
• Adders/Subtractors  
D
• General Logic Functions  
8
10  
11  
E
9
F
Description  
12  
G
The CD4030BMS types consist of four independent Exclu-  
sive-OR gates. The CD4030BMS provides the system  
designer with a means for direct implementation of the  
Exclusive-OR function.  
M
13  
H
The CD4030BMS is supplied in these 14-lead outline pack-  
ages:  
J = A  
K = C  
B
D
M = G  
L = E  
H
F
VSS = 7  
Braze Seal DIP H4H  
VDD = 14  
Frit Seal DIP  
H1B  
Ceramic Flatpack H3W  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 3305  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
7-317  

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