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EPM1270M256I5N PDF预览

EPM1270M256I5N

更新时间: 2024-02-14 16:39:49
品牌 Logo 应用领域
英特尔 - INTEL 输入元件可编程逻辑
页数 文件大小 规格书
88页 982K
描述
Flash PLD, 10ns, 980-Cell, CMOS, PBGA256, LEAD FREE, MICRO, FBGA-256

EPM1270M256I5N 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:BGA
包装说明:LEAD FREE, MICRO, FBGA-256针数:256
Reach Compliance Code:unknownECCN代码:3A991
HTS代码:8542.39.00.01风险等级:5.05
其他特性:IT CAN ALSO OPERATE AT 3.3V系统内可编程:YES
JESD-30 代码:R-PBGA-B256JESD-609代码:e1
JTAG BST:YES湿度敏感等级:3
专用输入次数:I/O 线路数量:212
宏单元数:980端子数量:256
组织:0 DEDICATED INPUTS, 212 I/O输出函数:MACROCELL
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA256,20X20,20封装形状:RECTANGULAR
封装形式:GRID ARRAY峰值回流温度(摄氏度):260
电源:1.5/3.3,2.5/3.3 V可编程逻辑类型:FLASH PLD
传播延迟:10 ns认证状态:Not Qualified
子类别:Programmable Logic Devices最大供电电压:2.625 V
最小供电电压:2.375 V标称供电电压:2.5 V
表面贴装:YES技术:CMOS
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:0.5 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:40Base Number Matches:1

EPM1270M256I5N 数据手册

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Section I. MAX II Device Family Data  
Sheet  
®
This section provides designers with the data sheet specifications for MAX II devices.  
The chapters contain feature definitions of the internal architecture, Joint Test Action  
Group (JTAG) and in-system programmability (ISP) information, DC operating  
conditions, AC timing parameters, and ordering information for MAX II devices.  
This section includes the following chapters:  
Chapter 1, Introduction  
Chapter 2, MAX II Architecture  
Chapter 3, JTAG and In-System Programmability  
Chapter 4, Hot Socketing and Power-On Reset in MAX II Devices  
Chapter 5, DC and Switching Characteristics  
Chapter 6, Reference and Ordering Information  
Revision History  
Refer to each chapter for its own specific revision history. For information about when  
each chapter was updated, refer to the Chapter Revision Dates section, which appears  
in the complete handbook.  
© August 2009 Altera Corporation  
MAX II Device Handbook  

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