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28F128W18 PDF预览

28F128W18

更新时间: 2022-04-23 23:00:11
品牌 Logo 应用领域
英特尔 - INTEL 闪存无线
页数 文件大小 规格书
100页 1116K
描述
Intel㈢ Wireless Flash Memory

28F128W18 数据手册

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Intel® Wireless Flash Memory (W18)  
28F320W18, 28F640W18, 28F128W18  
Datasheet  
Product Features  
High Performance Read-While-Write/  
Erase  
Architecture  
Multiple 4-Mbit Partitions  
Dual Operation: RWW or RWE  
8KB parameter blocks  
64KB main blocks  
Top or Bottom Parameter Devices  
16-bit wide data bus  
Burst frequency at 66 MHz  
60 ns Initial Access Read Speed  
11 ns Burst-Mode Read Speed  
20 ns Page-Mode Read Speed  
4-, 8-, 16-, and Continuous-Word Burst  
Mode Reads  
Burst and Page Mode Reads in all  
Blocks, across all partition boundaries  
Burst Suspend Feature  
Software  
—5 µs (typ.) Program and Erase Suspend  
Latency Time  
Flash Data Integrator (FDI) and Common  
Flash Interface (CFI) Compatible  
Programmable WAIT Signal Polarity  
Enhanced Factory Programming at  
3.1 µs/word (typ.for 0.13 µm)  
Security  
Packaging and Power  
0.13 µm: 32-, 64-, and 128-Mbit in VF  
BGA Package; 128-Mbit in QUAD+  
Package  
128-bit Protection Register  
64-bits Unique Programmed by Intel  
64-bits User-Programmable  
Absolute Write Protection with VPP at  
Ground  
Individual and Instantaneous Block  
Locking/Unlocking with Lock-Down  
Capability  
0.18 µm: 32- and 128-Mbit Densities in  
VF BGA Package; 64-Mbit Density in  
µBGA* Package  
56 Active Ball Matrix, 0.75 mm Ball-  
Pitch  
Quality and Reliability  
VCC = 1.70 V to 1.95 V  
VCCQ = 1.70 V to 2.24 V or 1.35 V to  
1.80 V  
Standby current (0.13 µm): 8µA (typ.)  
Read current: 7mA (typ.)  
Temperature Range: –40 °C to +85 °C  
100k Erase Cycles per Block  
0.13 µm ETOX™ VIII Process  
0.18 µm ETOX™ VII Process  
The Intel® Wireless Flash Memory (W18) device with flexible multi-partition dual operation,  
provides high-performance asynchronous and synchronous burst reads. It is an ideal memory for  
low-voltage burst CPUs. Combining high read performance with flash memory’s intrinsic non-  
volatility, the W18 device eliminates the traditional system-performance paradigm of shadowing  
redundant code memory from slow nonvolatile storage to faster execution memory. It reduces  
the total memory requirement that increases reliability and reduces overall system power  
consumption and cost.  
The W18 device’s flexible multi-partition architecture allows programming or erasing to occur  
in one partition while reading from another partition. This allows for higher data write  
throughput compared to single partition architectures. The dual-operation architecture also  
allows two processors to interleave code operations while program and erase operations take  
place in the background. The designer can also choose the size of the code and data partitions via  
the flexible multi-partition architecture.  
Notice: This document contains information on new products in production. The specifications  
are subject to change without notice. Verify with your local Intel sales office that you have the  
latest datasheet before finalizing a design.  
290701-009  
December 2003  

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