1-MBIT (128K x 8)
BOOT BLOCK FLASH MEMORY
28F001BX-T/28F001BX-B/28F001BN-T/28F001BN-B
Y
Y
High-Integration Blocked Architecture
High-Performance Read
Ð 70/75 ns, 90 ns, 120 ns, 150 ns
Maximum Access Time
Ð One 8 KB Boot Block w/Lock Out
Ð Two 4 KB Parameter Blocks
Ð One 112 KB Main Block
g
Ð 5.0V 10% V
CC
Y
Y
Y
Y
Y
100,000 Erase/Program Cycles Per
Block
Hardware Data Protection Feature
Ð Erase/Write Lockout during Power
Transitions
Simplified Program and Erase
Ð Automated Algorithms via On-Chip
Write State Machine (WSM)
Advanced Packaging, JEDEC Pinouts
Ð 32-Pin PDIP
Ð 32-Lead PLCC, TSOP
Y
Y
SRAM-Compatible Write Interface
Deep Power-Down Mode
ETOXTM II Nonvolatile Flash
Technology
Ð EPROM-Compatible Process Base
Ð High-Volume Manufacturing
Experience
Ð 0.05 mA I
Typical
CC
Ð 0.8 mA I Typical
PP
Y
g
12.0V 5% V
PP
Y
Extended Temperature Options
Intel’s 28F001BX-B and 28F001BX-T combine the cost-effectiveness of Intel standard flash memory with
features that simplify write and allow block erase. These devices aid the system designer by combining the
functions of several components into one, making boot block flash an innovative alternative to EPROM and
EEPROM or battery-backed static RAM. Many new and existing designs can take advantage of the
28F001BX’s integration of blocked architecture, automated electrical reprogramming, and standard processor
interface.
The 28F001BX-B and 28F001BX-T are 1,048,576 bit nonvolatile memories organized as 131,072 bytes of
8 bits. They are offered in 32-pin plastic DIP, 32-lead PLCC and 32-lead TSOP packages. Pin assignment
conform to JEDEC standards for byte-wide EPROMs. These devices use an integrated command port and
state machine for simplified block erasure and byte reprogramming. The 28F001BX-T’s block locations pro-
vide compatibility with microprocessors and microcontrollers that boot from high memory, such as Intel’s
MCS -186 family, 80286, i386TM, i486TM, i860TM and 80960CA. With exactly the same memory segmentation,
É
the 28F001BX-B memory map is tailored for microprocessors and microcontrollers that boot from low memory,
such as Intel’s MCS-51, MCS-196, 80960KX and 80960SX families. All other features are identical, and unless
otherwise noted, the term 28F001BX can refer to either device throughout the remainder of this document.
The boot block section includes a reprogramming write lock out feature to guarantee data integrity. It is
designed to contain secure code which will bring up the system minimally and download code to the other
locations of the 28F001BX. Intel’s 28F001BX employs advanced CMOS circuitry for systems requiring high-
performance access speeds, low power consumption, and immunity to noise. Its access time provides
no-WAIT-state performance for a wide range of microprocessors and microcontrollers. A deep-powerdown
mode lowers power consumption to 0.25 mW typical through V , crucial in laptop computer, handheld instru-
CC
mentation and other low-power applications. The RP power control input also provides absolute data protec-
tion during system powerup or power loss.
Ý
Manufactured on Intel’s ETOX process base, the 28F001BX builds on years of EPROM experience to yield the
highest levels of quality, reliability, and cost-effectiveness.
NOTE: The 28F001BN is equivalent to the 28F001BX.
*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
©
COPYRIGHT INTEL CORPORATION, 1995
November 1995
Order Number: 290406-007
5秒后页面跳转
MAX487芯片引脚图及功能、应用领域详解
IR2110驱动芯片引脚图及功能、电路图详解
74LS74是什么芯片 74LS74引脚图及功能表
CD4511芯片引脚图及功能、电路图解析
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
