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21154

更新时间: 2024-01-18 17:42:35
品牌 Logo 应用领域
英特尔 - INTEL PC
页数 文件大小 规格书
168页 1562K
描述
21154 PCI-to-PCI Bridge

21154 数据手册

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21154 PCI-to-PCI Bridge  
Datasheet  
Product Features  
Complies fully with the PCI Local Bus  
Specification, Revision 2.1  
Provides a 4-pin general-purpose I/O  
interface, accessible through device-  
specific configuration space  
Provides enhanced address decoding:  
—A 32-bit I/O address range  
Complies fully with the PCI Power  
Management Specification, Revision 1.01  
Supports 64-bit extension signals on the  
primary and secondary interfaces  
—A 32-bit memory-mapped I/O address  
range  
Implements delayed transactions for all PCI  
configuration, I/O, and memory read  
commands–up to three transactions  
simultaneously in each direction  
—A 64-bit prefetchable memory address  
range  
ISA-aware mode for legacy support in  
the first 64KB of I/O address range  
Allows 152 bytes of buffering (data and  
address) for upstream posted memory write  
commands and 88 bytes of buffering for  
downstream posted memory write  
commands—up to nine upstream and five  
downstream posted write transactions  
simultaneously  
— VGA addressing and VGA palette  
snooping support  
Includes live insertion support  
Supports PCI transaction forwarding for the  
following commands:  
Allows 152 bytes of read data buffering  
upstream and 152 bytes of read data  
buffering downstream  
All I/O and memory commands  
Type 1 to Type 1 configuration  
commands  
Provides concurrent primary and secondary  
bus operation to isolate traffic  
Type 1 to Type 0 configuration  
commands (downstream only)  
Provides ten secondary clock outputs:  
Low skew, permitting direct drive of  
option slots  
All Type 1 to special cycle configuration  
commands  
Individual clock disables, capable of  
automatic configuration during reset  
Includes downstream lock support  
Supports both 5-V and 3.3-V signaling  
Provides arbitration support for nine  
environments  
secondary bus devices:  
—A programmable 2-level arbiter  
Available in both 33 MHz and 66 Mhz  
versions  
Hardware disable control, permitting use  
of an external arbiter  
Provides an IEEE standard 1149.1 JTAG  
interface  
1. For the 21154–AB and later revisions only. The 21154–AA does not implement this feature.  
Order Number: 278108-002  
July 1999  

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