Datasheet > 21154-AE

21154-AE

更新时间： 2024-02-15 13:00:03

品牌	Logo	应用领域
英特尔 - INTEL		时钟 PC 外围集成电路
页数	文件大小	规格书
168页	727K
描述
PCI Bus Controller, CMOS, PBGA304, PLASTIC, BGA-304

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21154-AE 技术参数

生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	BGA, BGA304,23X23,50	针数：	304
Reach Compliance Code：	compliant	ECCN代码：	3A991.A.2
HTS代码：	8542.31.00.01	风险等级：	5.83
最大时钟频率：	33 MHz	JESD-30 代码：	S-PBGA-B304
长度：	31 mm	端子数量：	304
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装等效代码：	BGA304,23X23,50	封装形状：	SQUARE
封装形式：	GRID ARRAY	电源：	3.3 V
认证状态：	Not Qualified	座面最大高度：	2.54 mm
子类别：	Bus Controllers	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	BALL
端子节距：	1.27 mm	端子位置：	BOTTOM
宽度：	31 mm	uPs/uCs/外围集成电路类型：	BUS CONTROLLER, PCI
Base Number Matches：	1

21154-AE 数据手册

21154 PCI-to-PCI Bridge

Datasheet

Product Features

■ Complies fully with the PCI Local Bus

Specification, Revision 2.1

■ Provides a 4-pin general-purpose I/O

interface, accessible through device-

specific configuration space

■ Provides enhanced address decoding:

—A 32-bit I/O address range

■ Complies fully with the PCI Power

Management Specification, Revision 1.0¹

■ Supports 64-bit extension signals on the

primary and secondary interfaces

—A 32-bit memory-mapped I/O address

range

■ Implements delayed transactions for all PCI

configuration, I/O, and memory read

commands–up to three transactions

simultaneously in each direction

—A 64-bit prefetchable memory address

range

—ISA-aware mode for legacy support in

the first 64KB of I/O address range

■

Allows 152 bytes of buffering (data and

address) for upstream posted memory write

commands and 88 bytes of buffering for

downstream posted memory write

commands—up to nine upstream and five

downstream posted write transactions

simultaneously

— VGA addressing and VGA palette

snooping support

■ Includes live insertion support

■ Supports PCI transaction forwarding for the

following commands:

■ Allows 152 bytes of read data buffering

upstream and 152 bytes of read data

buffering downstream

—All I/O and memory commands

—Type 1 to Type 1 configuration

commands

■ Provides concurrent primary and secondary

bus operation to isolate traffic

—Type 1 to Type 0 configuration

commands (downstream only)

■ Provides ten secondary clock outputs:

—Low skew, permitting direct drive of

option slots

—All Type 1 to special cycle configuration

commands

—Individual clock disables, capable of

automatic configuration during reset

■ Includes downstream lock support

■ Supports both 5-V and 3.3-V signaling

■ Provides arbitration support for nine

environments

secondary bus devices:

—A programmable 2-level arbiter

■ Available in both 33 MHz and 66 Mhz

versions

—Hardware disable control, permitting use

of an external arbiter

■ Provides an IEEE standard 1149.1 JTAG

interface

^1.For the 21154–AB and later revisions only. The 21154–AA does not implement this feature.

Order Number: 278108-002

July 1999

12 3 4 5 6 7...168

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