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21150-AB PDF预览

21150-AB

更新时间: 2024-02-13 09:45:53
品牌 Logo 应用领域
英特尔 - INTEL 时钟PC外围集成电路
页数 文件大小 规格书
164页 811K
描述
PCI Bus Controller, CMOS, PQFP208, PLASTIC, QFP-208

21150-AB 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:FQFP, QFP208,1.2SQ,20
针数:208Reach Compliance Code:unknown
ECCN代码:3A991.A.2HTS代码:8542.31.00.01
风险等级:5.85地址总线宽度:32
最大时钟频率:33 MHz外部数据总线宽度:32
JESD-30 代码:S-PQFP-G208JESD-609代码:e0
长度:28 mm端子数量:208
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:FQFP
封装等效代码:QFP208,1.2SQ,20封装形状:SQUARE
封装形式:FLATPACK, FINE PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3,3.3/5 V认证状态:Not Qualified
座面最大高度:3.75 mm子类别:Bus Controllers
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:28 mm
uPs/uCs/外围集成电路类型:BUS CONTROLLER, PCIBase Number Matches:1

21150-AB 数据手册

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21150 PCI-to-PCI Bridge  
Preliminary Datasheet  
Product Features  
Complies fully with the PCI Local Bus  
Provides a 4-pin general-purpose I/O  
interface, accessible through device-  
specific configuration space  
Specification, Revision 2.1  
Complies fully with the Advanced  
Configuration Power Interface (ACPI)  
Specification  
Provides enhanced address decoding:  
—A 32-bit I/O address range  
Complies fully with the PCI Power  
— A 32-bit memory-mapped I/O address  
range  
Management Specification, Revision 1.01  
Complies fully with Revision 1.0 of the  
PCI-to-PCI Bridge Architecture  
Specification  
— A 64-bit prefetchable memory address  
range  
— ISA-aware mode for legacy support in  
the first 64KB of I/O address range  
Implements delayed transactions for all PCI  
configuration, I/O, and memory read  
commands—up to three transactions  
simultaneously in each direction  
— VGA addressing and VGA palette  
snooping support  
Allows 88 bytes of buffering (data and  
address) for posted memory write  
commands in each direction—up to five  
posted write transactions simultaneously in  
each direction  
Includes live insertion support  
Supports PCI transaction forwarding for the  
following commands:  
— All I/O and memory commands  
Allows 72 bytes of read data buffering in  
— Type 1 to Type 1 configuration  
commands  
each direction  
Provides concurrent primary and secondary  
— Type 1 to Type 0 configuration  
commands (downstream only)  
bus operation, to isolate traffic  
Provides 10 secondary clock outputs with  
— All Type 1 to special cycle  
configuration commands  
the following features:  
Low skew permits direct drive of option  
slots  
Includes downstream lock support  
Supports both 5-V and 3.3-V signaling  
Individual clock disables, capable of  
automatic configuration during reset  
environments  
Available in both 33 MHz and 66 MHz  
Provides arbitration support for nine  
versions  
secondary bus devices:  
Provides an IEEE standard 1149.1 JTAG  
— A programmable 2-level arbiter  
interface.  
— Hardware disable control, to permit use  
of an external arbiter  
1.For 21150-AB and later revisions only. The 21150-AA does not implement this feature.  
Notice: This document contains preliminary information on new products in production. The  
specifications are subject to change without notice. Verify with your local Intel sales office that  
you have the latest datasheet before finalizing a design.  
Order Number: 278106-002  
July 1998  

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