Datasheet > IN74AC109N

IN74AC109N

更新时间： 2024-11-26 05:39:19

品牌	Logo	应用领域
IKSEMICON		触发器栅
页数	文件大小	规格书
6页	233K
描述
Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS

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IN74AC109N 数据手册

TECHNICAL DATA

IN74AC109

Dual J-K Flip-Flop

with Set and Reset

High-Speed Silicon-Gate CMOS

The IN74AC109 is identical in pinout to the LS/ALS109,HC/HCT109.

The device inputs are compatible with standard CMOS outputs, with

pullup resistors, they are compatible with LS/ALS outputs.

This device consists of two J-K flip-flops with individual set, reset,

and clock inputs. Changes at the inputs are reflected at the outputs with

the next low-to-high transition of the clock. Both Q to Q outputs are

available from each flip-flop.

ORDERING INFORMATION

IN74AC109N Plastic

IN74AC109D SOIC

T_A= -40° to 85° C for all packages

•

Outputs Directly Interface to CMOS, NMOS, and TTL

Operating Voltage Range: 2.0 to 6.0 V

Low Input Current: 1.0 μA; 0.1 μA @ 25°C

High Noise Immunity Characteristic of CMOS Devices

Outputs Source/Sink 24 mA

PIN ASSIGNMENT

LOGIC DIAGRAM

FUNCTION TABLE

Inputs

Clock

Outputs

Set Reset

H^*

Toggle

No Change

PIN 16=V_CC

PIN 8 = GND

X = Don’t care

^*Both outputs will remain high as long as Set and

Reset are low, but the output states are

unpredictable if Set and Reset go high

simultaneously.

Rev. 00

12 3 4 5 6

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