Datasheet > IN7472D

IN7472D

更新时间： 2024-11-26 05:39:19

品牌	Logo	应用领域
IKSEMICON		栅
页数	文件大小	规格书
5页	314K
描述
AND-Gated J-K Master-Slave Flip- Flops with Reset and Clear

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IN7472D 数据手册

TECHNICAL DATA

IN7472

AND-Gated J-K Master-Slave Flip-

Flops with Reset and Clear

LOGIC DIAGRAM

ORDERING INFORMATION

IN7472N Plastic

IN7472D SOIC

T_A= -10° to 70° C for all packages

PIN ASSIGNMENT

PIN 14 =V_CC

PIN 7 = GND

NC - No internal connection

FUNCTION TABLE

Inputs

Output

Reset Clear Clock

H^*

Q₀

H^*

Q₀

TOGGLE

X =don’t care

Q₀= the level of Q before the indicated input conditions were established.

TOGGLE: Each output changes to the complement of its previous level on each

active transition (pulse) of the clock.

^*This configuration is nonstable; that is, it will not persist whenpreset and clear inputs

return to their inactive (high) level.

12 3 4 5

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型号	品牌	获取价格	描述	数据表
IN7472N	INTEGRAL	获取价格	AND-Gated J-K Master-Slave Flip-Flops with Reset and Clear
IN7472N	IKSEMICON	获取价格	AND-Gated J-K Master-Slave Flip- Flops with Reset and Clear
IN74AC00	INTEGRAL	获取价格	Quad 2-Input NAND Gate High-Speed Silicon-Gate CMOS
IN74AC00N	INTEGRAL	获取价格	Gate
IN74AC02	INTEGRAL	获取价格	Quad 2-Input NOR Gate High-Speed Silicon-Gate CMOS
IN74AC02D	INTEGRAL	获取价格	Quad 2-Input NOR Gate High-Speed Silicon-Gate CMOS
IN74AC02N	INTEGRAL	获取价格	Quad 2-Input NOR Gate High-Speed Silicon-Gate CMOS
IN74AC04	INTEGRAL	获取价格	Hex Inverter High-Speed Silicon-Gate CMOS
IN74AC04D	INTEGRAL	获取价格	Hex Inverter High-Speed Silicon-Gate CMOS
IN74AC04N	INTEGRAL	获取价格	Hex Inverter High-Speed Silicon-Gate CMOS