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IHLP5050CEER100M07 PDF预览

IHLP5050CEER100M07

更新时间: 2024-09-15 22:58:51
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威世 - VISHAY /
页数 文件大小 规格书
4页 132K
描述
FIXED IND 10UH 7A 30.86 MOHM SMD

IHLP5050CEER100M07 数据手册

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IHLP-5050CE-07  
www.vishay.com  
Vishay Dale  
IHLP® Commercial Inductors, High Saturation Series,  
5 % DCR Tolerance  
FEATURES  
• Lowest height (3.5 mm) in this package footprint  
• Shielded construction  
• Frequency range up to 5.0 MHz  
• Lowest DCR/μH, in this package size  
• Handles high transient current spikes without  
saturation  
• Ultra low buzz noise, due to composite construction  
• IHLP design. PATENT(S): www.vishay.com/patents  
• Material categorization: for definitions of compliance  
please see www.vishay.com/doc?99912  
DESIGN SUPPORT TOOLS click logo to get started  
APPLICATIONS  
• Tolerance DCR for current sense applications  
• Improved current balance in phased power supplies  
• Improved thermal management  
Models  
Design Tools  
Available  
Available  
• PDA / notebook / desktop / server and battery powered  
devices  
STANDARD ELECTRICAL SPECIFICATIONS  
• High current, low profile POL converters  
• DC/DC converters in distributed power systems  
L0  
HEAT  
RATING  
CURRENT  
DC TYP.  
(A) (1)  
DC/DC converter for Field Programmable Gate Array (FPGA)  
INDUCTANCE  
ꢀ0 % AT 100 kHz,  
0.ꢀ5 V, 0 A  
(μH)  
DCR  
5 %  
AT ꢀ5 °C  
(mΩ)  
SATURATION  
CURRENT  
DC TYP.  
DIMENSIONS in inches [millimeters]  
(A) (ꢀ)  
Typical Pad Layout  
0.50ꢁ  
0.5ꢁ0  
[14.732ꢀ  
0.60  
0.68  
1.0  
1.5  
2.2  
3.3  
4.7  
5.6  
10  
1.85  
2.34  
29  
28  
24  
19  
16  
12  
10  
9.5  
7
51  
49  
40  
35  
29  
27  
24  
19  
14  
[12.9ꢀ  
ꢂaꢃ.  
0.195  
[4.95ꢀ  
3.21  
0.325  
0.13ꢁ  
[3.5ꢀ ꢂaꢃ.  
[ꢁ.255ꢀ  
0.091 0.01  
[2.3 0.3ꢀ  
4.97  
7.20  
0.1ꢁ5 0.01  
[4.7 0.3ꢀ  
10.69  
14.27  
18.19  
30.86  
The diagram applies to  
values 0.6 µH and below.  
0.520 0.015  
[13.2 0.3ꢁꢀ ꢂaꢃ.  
Typical Pad Layout  
0.50ꢁ  
[12.9ꢀ  
ꢂaꢃ.  
0.575  
[14.605ꢀ  
Notes  
All test data is referenced to 25 °C ambient  
Operating temperature range -55 °C to +125 °C  
The part temperature (ambient + temp. rise) should not exceed  
125 °C under worst case operating conditions. Circuit design,  
component placement, PWB trace size and thickness, airflow  
and other cooling provisions all affect the part temperature. Part  
temperature should be verified in the end application  
0.12ꢁ [3.3ꢀ  
0.325  
[ꢁ.255ꢀ  
0.13ꢁ  
[3.5ꢀ ꢂaꢃ.  
0.0ꢁ7 0.01  
[2.2 0.254ꢀ  
0.11ꢁ 0.01  
[3.0 0.3ꢀ  
Rated operating voltage (across inductor) = 75 V  
DC current (A) that will cause an approximate ΔT of 40 °C  
DC current (A) that will cause L0 to drop approximately 20 %  
(1)  
(2)  
The diagram applies to  
values 0.6ꢁ µH and above.  
0.520 0.015  
[13.2 0.3ꢁꢀ  
DESCRIPTION  
1.0 μH  
IHLP-5050CE-07  
ꢀ0 %  
INDUCTANCE TOLERANCE  
ER  
e3  
MODEL  
INDUCTANCE VALUE  
PACKAGE CODE JEDEC® LEAD (Pb)-FREE STANDARD  
GLOBAL PART NUMBER  
I
H
L
P
5
0
5
0
C
E
E
R
1
R
0
M
0
7
PACKAGE  
CODE  
INDUCTANCE  
VALUE  
PRODUCT FAMILY  
SIZE  
TOL.  
SERIES  
PATENT(S): www.vishay.com/patents  
This Vishay product is protected by one or more United States and international patents.  
Revision: 14-Jul-17  
Document Number: 34166  
1
For technical questions, contact: magnetics@vishay.com  
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT  
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000  

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