Datasheet > IDTQS5LV919-133Q

IDTQS5LV919-133Q

更新时间： 2023-07-15 00:00:00

品牌	Logo	应用领域
艾迪悌 - IDT		光电二极管
页数	文件大小	规格书
12页	111K
描述
PLL Based Clock Driver, 5LV Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PDSO28, QSOP-28

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IDTQS5LV919-133Q 数据手册

QS5LV919

INDUSTRIALTEMPERATURERANGE

3.3VLOWSKEWCMOSPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER

3.3V LOW SKEW CMOS PLL

CLOCK DRIVER WITH

QS5LV919

INTEGRATED LOOP FILTER

FEATURES:

DESCRIPTION:

• 3.3V operation

The QS5LV919 Clock Driver uses an internal phase locked loop

(PLL) to lock low skew outputs to one of two reference clock inputs.

Eight outputs are available: 2xQ, Q0-Q4, Q5, Q/2. Careful layout and

design ensure < 300 ps skew between the Q0-Q4, and Q/2 outputs.

The QS5LV919 includes an internal RC filter which provides excellent

jitter characteristics and eliminates the need for external components.

Various combinations of feedback and a divide-by-2 in the VCO path

allow applications to be customized for linear VCO operation over a

wide range of input SYNC frequencies. The PLL can also be disabled

by the PLL_EN signal to allow low frequency or DC testing. The LOCK

output asserts to indicate when phase lock has been achieved. The

QS5LV919 is designed for use in high-performance workstations, multi-

board computers, networking hardware, and mainframe systems. Sev-

eral can be used in parallel or scattered throughout a system for guar-

anteed low skew, system-wide clock distribution networks.

• JEDEC compatible LVTTL level outputs

• Clock inputs are 5V tolerant

• < 300ps output skew, Q0–Q4

• 2xQ output, Q outputs, Q output, Q/2 output

• Outputs 3-state and reset while OE/RST low

• PLL disable feature for low frequency testing

• Internal loop filter RC network

• Functional equivalent to MC88LV915, IDT74FCT388915

• Positive or negative edge synchronization (PE)

• Balanced drive outputs ±24mA

• 160MHz maximum frequency (2xQ output)

• Available in QSOP and PLCC packages

For more information on PLL clock driver products, see Application

Note AN-227.

FUNCTIONALBLOCKDIAGRAM

REF_SEL

FEEDBACK

PLL_EN

FREQ_SEL

LOCK

SYNC0

SYNC1

PHASE

LOOP

FILTER

VCO

DETECTOR

OE/RST

Q/2

2xQ

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

INDUSTRIAL TEMPERATURE RANGE

FEBRUARY 2006

2006 Integrated Device Technology, Inc.

DSC-5820/7

12 3 4 5 6 7...12

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与IDTQS5LV919-133Q相关器件

型号	品牌	获取价格	描述	数据表
IDTQS5LV919-160Q	IDT	获取价格	PLL Based Clock Driver, 5LV Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PDSO28,
IDTQS5LV919-55J	IDT	获取价格	PLL Based Clock Driver, 5LV Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PQCC28,
IDTQS5LV919-55Q	IDT	获取价格	PLL Based Clock Driver, 5LV Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PDSO28,
IDTQS5LV919-70J	IDT	获取价格	PLL Based Clock Driver, 5LV Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PQCC28,
IDTQS5LV931-50Q8	IDT	获取价格	PLL Based Clock Driver, 6 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, QSOP-20
IDTQS5LV931-66Q	IDT	获取价格	PLL Based Clock Driver, 5LV Series, 6 True Output(s), 0 Inverted Output(s), CMOS, PDSO20,
IDTQS5LV931-66Q8	IDT	获取价格	PLL Based Clock Driver, 6 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, QSOP-20
IDTQS5LV931-80Q	IDT	获取价格	PLL Based Clock Driver, 5LV Series, 6 True Output(s), 0 Inverted Output(s), CMOS, PDSO20,
IDTQS5LV931-80Q8	IDT	获取价格	PLL Based Clock Driver, 6 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, QSOP-20
IDTQS74153ATQ	IDT	获取价格	HIGH-SPEED CMOS DUAL 4-INPUT MULTIPLEXER

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