Datasheet > IDTCV169NL

IDTCV169NL

更新时间： 2024-11-17 07:25:27

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
20页	117K
描述
Processor Specific Clock Generator, 400MHz, VFQFPN-64

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数据手册

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IDTCV169NL 数据手册

IDTCV169

COMMERCIALTEMPERATURERANGE

PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR

PROGRAMMABLE FLEXPC

CLOCK FOR P4 PROCESSOR

IDTCV169

DESCRIPTION:

FEATURES:

IDTCV169isa64pinclockdevice,complyingwithIntelCK410Mrequirements

forInteladvanceP4processors.TheCPUoutputbufferisdesignedtosupport

upto400MHzprocessor. ThisdevicealsoimplementsBand-gapreferenced

IREF to reduce the impact of VDD variation on differential outputs, which can

providemorerobustsystemperformance.

• Power management control suitable for notebook applications

• One high precision PLL for CPU/SRC/PCI, SSC and N program-

ming

• One high precision PLL for 96MHz/48MHz

• Band-gap circuit for differential outputs

• Support spread spectrum modulation, –0.5 down spread and

others

• Support SMBus block read/write, index read/write

• Selectable output strength

• Smooth transition for N programming

• Available in VFQFPN package

OUTPUTS:

• 2*0.7V current –mode differential CPU CLK pair

• 9*0.7V current –mode differential SRC CLK pair

• One CPU_ITP/SRC selectable CLK pair

• 5*PCI, 1 free running, 33.3MHz

• 1*96MHz,1*48MHz

KEYSPECIFICATIONS:

• CPU CLK cycle to cycle jitter < 85ps

• PCI CLK cycle to cycle jitter < 250ps

• 1*REF

FUNCTIONALBLOCKDIAGRAM

CPU[1:0]

CPU CLK

Output Buffer

PLL1

SSC

N Programmable

Stop Logic

XTAL_IN

XTAL

CPU_ITP/SRC7

IREF

Osc Amp

REF

XTAL_OUT

ITP_EN

SDATA

SM Bus

SRC CLK

Controller

Output Buffer

SCLK

SRC[10:8], [6:5], [3:0]

Stop Logic

PCI[3:0], PCIF0

VTT_PWRGD#/PD

IREF

OE6#, OE3#,

OE1#, OE0#

OE[B:A]#

Control

48MHz

Logic

48MHz/96MHz

Output BUffer

FSA.B.C

PLL2

PCI_STOP#

CPU_STOP#

DOT96

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

COMMERCIAL TEMPERATURE RANGE

AUGUST 2005

DSC 6903/2

12 3 4 5 6 7...20

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