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IDT88P8341BHGI

更新时间： 2024-09-17 19:36:11
品牌 Logo 应用领域
艾迪悌 - IDT 外围集成电路
页数 文件大小 规格书
96页 536K
描述
Microprocessor Circuit, CMOS, PBGA820

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中文翻译

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IDT88P8341BHGI 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：BGA针数：820
Reach Compliance Code：unknown风险等级：5.81
JESD-30 代码：S-PBGA-B820端子数量：820
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA820,34X34,40封装形状：SQUARE
封装形式：GRID ARRAY电源：1.8,3.3 V
认证状态：Not Qualified子类别：Other Microprocessor ICs
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
uPs/uCs/外围集成电路类型：MICROPROCESSOR CIRCUITBase Number Matches：1

IDT88P8341BHGI 数据手册

 浏览型号IDT88P8341BHGI的Datasheet PDF文件第2页浏览型号IDT88P8341BHGI的Datasheet PDF文件第3页浏览型号IDT88P8341BHGI的Datasheet PDF文件第4页浏览型号IDT88P8341BHGI的Datasheet PDF文件第5页浏览型号IDT88P8341BHGI的Datasheet PDF文件第6页浏览型号IDT88P8341BHGI的Datasheet PDF文件第7页 
SPI EXCHANGESPI-3TOSPI-4  
Issue1.0  
IDT88P8341  
- Number of errors  
- Number of bytes  
• Green parts available, see ordering information  
FEATURES  
• Functionality  
- Low speed to high speed SPI exchange device  
- Logical port (LP) mapping (SPI-3 <-> SPI-4) tables per direction  
- Per LP configurable memory allocation  
- Maskable interrupts for fatal errors  
- Fragment and burst length configurable per interface: min 16 bytes,  
max 256 bytes  
• Standard Interfaces  
- OIF SPI-3: 8 or 32 bit, 19.44-133 MHz, 256 address range, 64  
concurrently active LPs per interface  
APPLICATIONS  
• Ethernet transport  
• SONET / SDH packet transport line cards  
• Broadband aggregation  
• Multi-service switches  
• IP services equipment  
- One OIF SPI-4 phase 2: 80 - 400 MHz, 256 address range, 64  
concurrently active LPs  
- SPI-4 FIFO status channel options:  
• LVDS full-rate  
• LVTTL eighth-rate  
- Compatible with Network Processor Streaming Interface (NPSI)  
NPE-Framer mode of operation  
- SPI-4 ingress LVDS automatic bit alignment and lane de-skew over  
the entire frequency range  
DESCRIPTION  
TheIDT88P8341isaSPI(SystemPacketInterface)ExchangewithaSPI-  
3interfaceandaSPI-4interface. Thedatathatenteronthelowspeedinterface  
(SPI-3)aremappedtologicalidentifiers(LIDs)andenqueuedfortransmission  
overthe highspeedinterface (SPI-4). The data thatenteronthe highspeed  
interface (SPI-4) are mapped to logical identifiers (LIDs) and enqueued for  
transmissionoverthelowspeedinterface(SPI-3).AdataflowbetweenSPI-  
3 and SPI-4 interfaces is accomplished with LID maps. The logical port  
addresses and number of entries in the LID maps may be dynamically  
configured.Variousparametersofadataflowmaybeconfiguredbytheuser  
such as buffer memory size and watermarks. In a typical application, the  
IDT88P8341 enables connection of a SPI-3 device to a SPI-4 network  
processor.InotherapplicationsaSPI-4devicemaybeconnectedtoaSPI-3  
networkprocessorortrafficmanager.  
- SPI-4 egress LVDS programmable lane pre-skew 0.1 to 0.3 cycle  
- IEEE 1149.1 JTAG  
- Serial or parallel microprocessor interface for control and monitoring  
•
Full Suite of Performance Monitoring Counters  
- Number of packets  
- Number of fragments  
FUNCTIONALBLOCKDIAGRAM  
SPI-3 to SPI-4 PFP  
SPI-4  
64 Logical  
Ports  
SPI-3  
64 Logical Ports  
SPI-4 to SPI-3 PFP  
Uproc IF  
Clock Generator  
JTAG IF  
Control Path  
Data Path PFP = Packet Fragment Processor  
6372 drw01  
IDTandtheIDTlogoaretrademarksofIntegratedDeviceTechnology,Inc  
APRIL 2006  
INDUSTRIAL TEMPERATURE RANGE  
1
2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-6372/9  
1234567...96

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