Datasheet > IDT82V3011PV

IDT82V3011PV

更新时间： 2022-12-12 13:49:53

品牌	Logo	应用领域
艾迪悌 - IDT		输入元件
页数	文件大小	规格书
30页	397K
描述
T1/E1/OC3 WAN PLL WITH SINGLE REFERENCE INPUT

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IDT82V3011PV 数据手册

T1/E1/OC3 WAN PLL WITH

SINGLE REFERENCE INPUT

IDT82V3011

•

Holdover frequency accuracy of 0.025 ppm

FEATURES

Phase slope of 5 ns per 125 µs

Attenuates wander from 2.1 Hz

Fast lock mode

Provides Time Interval Error (TIE) correction

MTIE of 600 ns

•

Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum

4 Enhanced and Stratum 4 timing for DS1 interfaces

Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing

for E1 interface

Selectable input reference: 8 kHz, 1.544 MHz, 2.048 MHz or 19.44

MHz

Provides C1.5o, C3o, C2o, C4o, C6o, C8o, C16o, C19o and C32o

output clock signals

Provides 7 types of 8 kHz framing pulses: F0o, F8o, F16o, F19o,

F32o, RSP and TSP

JTAG boundary scan

Holdover status indication

Freerun status indication

Normal status indication

Lock status indication

Input reference quality indication

3.3 V operation with 5 V tolerant I/O

Package available: 56-pin SSOP

Provides a C2/C1.5 output clock signal with the frequency

controlled by the reference input Fref

FUNCTIONAL BLOCK DIAGRAM

TDO TDI

OSCi

TCLR

RST

V_DDV_SSV_DDV_SSV_DDV_SSV_DDV_SS

C2/C1.5

C32o

C19o

TCK

TMS

JTAG

OSC

C19POS

C19NEG

TRST

C16o

C8o

C4o

C2o

FLOCK

Fref

C3o

C1.5o

C6o

Virtual

DPLL

TIE Control

Block

Reference

F0o

F8o

F16o

F19o

F32o

RSP

TSP

Invalid Input

Signal

Detection

Reference

Input Monitor

MON_out

Feedback Signal

LOCK

Input Frequency

Selection

State Control Circuit

TIE_en MODE_sel1 MODE_sel0 Normal Holdover Freerun

F_sel1 F_sel0

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

OCTOBER 22, 2003

INDUSTRIAL TEMPERATURE RANGE

DSC-6237/3

2003 Integrated Device Technology, Inc.

12 3 4 5 6 7...30

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