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IDT77301L12PFI8 PDF预览

IDT77301L12PFI8

更新时间: 2024-02-07 06:20:44
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
29页 337K
描述
FIFO, 128X9, 10ns, Synchronous, PQFP100, TQFP-100

IDT77301L12PFI8 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:LFQFP,针数:100
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.78
最长访问时间:10 ns周期时间:16 ns
JESD-30 代码:S-PQFP-G100JESD-609代码:e0
长度:14 mm内存密度:1152 bit
内存宽度:9功能数量:1
端子数量:100字数:128 words
字数代码:128工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:128X9可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD宽度:14 mm
Base Number Matches:1

IDT77301L12PFI8 数据手册

 浏览型号IDT77301L12PFI8的Datasheet PDF文件第2页浏览型号IDT77301L12PFI8的Datasheet PDF文件第3页浏览型号IDT77301L12PFI8的Datasheet PDF文件第4页浏览型号IDT77301L12PFI8的Datasheet PDF文件第5页浏览型号IDT77301L12PFI8的Datasheet PDF文件第6页浏览型号IDT77301L12PFI8的Datasheet PDF文件第7页 
UTOPIAꢀIꢀO™  
1 TO 4  
IDT77301  
(128 X 9 X 4)  
DEMULTIPLEXER-ꢀIꢀO  
ꢀeatures:  
Datatransfersonfixedcellsizes  
GeneralDescription  
The IDT77301 UtopiaFIFO is a high-speed, low power single input  
port supplying four demultiplexing FIFO output ports. Each of the four  
outputsynchronous(clocked)FIFOsare64words(128bytes)indepth.  
Dataiswrittentotheinputportincells”(fixedlengthdatapackets).The  
cellsizeisprogrammablefrom16bytesto128bytes.  
Theinputportcanbeconfiguredtosupport9-bitor18-bitwidedata  
buses. (Multiple77301scanbeconfiguredtohandle32and64-bitbuses  
withnoadditionallogic.)  
Therearefourroutingmethodsthat canbeusedtotransferdatatothe  
77301.Twomethodsuseout-bandroutingfortheportselection,which  
requires use ofthe Address Locationbus. The remainingtwomethods  
supportin-bandrouting,whichusestheAddressLocationbusinconjunc-  
tionwiththeDatabusforportselection.Utopia2signalingsupportssingle  
celltransferstosingleoutputports,butthe77301alsooffersaproprietary  
multicastingprotocol.Multicastingenablesasinglecelltobetransferred  
simultaneouslytomultipleselectedoutputports.  
Programmablecellsize  
Oneinputporttofouroutputports  
Four Independent output 128 x 9 FIFO Queues  
Selectableeighteenbitorninebitinputbus  
Selectableeight/ninebitorfourbitoutputbuses  
ProgrammablechipIdentification  
“UtopiaTx”level2compliantinputinterfacesignaling  
“UtopiaTx”level1compliantoutputinterfacesignaling  
Separateclocksforinputandoutput  
SelectableIn-bandorOut-bandrouting  
Multicastcapability  
Dataclockratesto62.5MHz,10nsaccesstime  
BuildingBlockImplementationallowsupto32outputchannelswith  
a 18, 36 or 64-bit input bus  
Four 562 Mbps output channels can be derived from a single  
1.1256Gbpsinputchannelwithnoadditionalgluelogic  
100-pin TQPF package  
The four output ports can be configured as 9-bit or 4-bit wide data  
buses. (18-bitwidebusescanbesupportedwithmultiple77301swithno  
ꢀunctionalBlockDiagram  
SOCS - a  
128 BYTE  
FIFO  
ENS  
CLAVS - a  
- a  
Data - a (D0-D8)  
RMS  
MAS  
SOCS - b  
128 BYTE  
FIFO  
ENS  
CLAVS - b  
- b  
BSS  
ADR (0-4)  
SOCR  
Data - b (D0-D8)  
SOCS - c  
ENR  
CLAVR  
128 BYTE  
FIFO  
ENS - c  
CLAVS - c  
Data - c (D0-D8)  
Data (D0-D17)  
WCLK  
SOCS - d  
128 BYTE  
FIFO  
ENS  
- d  
CLAVS - d  
Data - d (D0-D8)  
RST  
MSE  
BNE  
RCLK  
SLE  
SCLK  
SDI/P_ID0  
3240 drw 01  
CONTROL  
REGISTER  
OE  
MARCH 2001  
1
DSC-3240/3  
©2001IntegratedDeviceTechnology,Inc.  

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