IDT74SSTVF16859

更新时间： 2024-11-11 04:58:31

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
7页	68K
描述
13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O

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数据手册

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IDT74SSTVF16859 数据手册

IDT74SSTVF16859

COMMERCIALTEMPERATURERANGE

13-BITTO26-BITREGISTEREDBUFFERWITHSSTLI/O

13-BIT TO 26-BIT REGISTERED IDT74SSTVF16859

BUFFER WITH SSTL I/O

FEATURES:

DESCRIPTION:

• 1:2 register buffer

The SSTVF16859 is a 13-bit to 26-bit registered buffer designed for

• Meets or exceeds JEDEC standard SSTVF16859

• 2.3V to 2.7V Operation for PC1600, PC2100, and PC2700

• 2.5V to 2.7V Operation for PC3200

2.3V-2.7VVDD forPC1600-PC2700and2.5V-2.7VVDD forPC3200, and

supports low standby operation. All data inputs and outputs are SSTL_2

level compatible with JEDEC standard for SSTL_2.

• SSTL_2 Class I style data inputs/outputs

• Differential CLK input

• RESET control compatible with LVCMOS levels

• Latch-up performance exceeds 100mA

• ESD >2000V per MIL-STD-883, Method 3015; >200V using

machine model (C = 200pF, R = 0)

• Available in 56 pin VFQFPN and 64 pin TSSOP packages

RESETisanLVCMOSinputsinceitmustoperatepredictablyduringthe

power-upphase.RESET,whichcanbeoperatedindependentofCLKand

CLK, must be held in the low state during power-up in order to ensure

predictable outputs (low state) before a stable clock has been applied.

RESET, when in the low state, will disable all input receivers, reset all

registers,andforcealloutputstoalowstate,beforeastableclockhasbeen

applied. Withinputsheldlowandastableclockapplied,outputswillremain

low during the Low-to-High transition of RESET.

APPLICATIONS:

• Along with CSPT857C, Zero Delay PLL Clock buffer, provides

complete solution for DDR1 DIMMs

FUNCTIONALBLOCKDIAGRAM

RESET

CLK

VREF

Q^1A

Q1B

TO 12 OTHER CHANNELS

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

COMMERCIAL TEMPERATURE RANGE

AUGUST 2003

2003 Integrated Device Technology, Inc.

DSC-6194/13

12 3 4 5 6 7

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与IDT74SSTVF16859相关器件

型号	品牌	获取价格	描述	数据表
IDT74SSTVF16859NL	IDT	获取价格	13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
IDT74SSTVF16859NLG	IDT	获取价格	13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
IDT74SSTVF16859PA	IDT	获取价格	13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
IDT74SSTVF16859PAG	IDT	获取价格	13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
IDT74SSTVF16859PAG8	IDT	获取价格	D Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 13-Bit, True Output, CMOS, PDSO
IDT74SSTVM16859NL8	IDT	获取价格	D Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 13-Bit, True Output, PQCC56, TH
IDT74SSTVN16859	IDT	获取价格	13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
IDT74SSTVN16859C	IDT	获取价格	13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
IDT74SSTVN16859CNL	IDT	获取价格	13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
IDT74SSTVN16859CNLG	IDT	获取价格	13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O