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IDT74LVCH162721APV8 PDF预览

IDT74LVCH162721APV8

更新时间: 2024-02-10 21:59:59
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
6页 65K
描述
Bus Driver, LVC/LCX/Z Series, 1-Func, 20-Bit, True Output, CMOS, PDSO56, SSOP-56

IDT74LVCH162721APV8 技术参数

生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP,针数:56
Reach Compliance Code:unknown风险等级:5.84
其他特性:WITH CLOCK ENABLE系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-G56JESD-609代码:e0
长度:18.415 mm逻辑集成电路类型:BUS DRIVER
位数:20功能数量:1
端口数量:2端子数量:56
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE WITH SERIES RESISTOR输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
传播延迟(tpd):6.6 ns认证状态:Not Qualified
座面最大高度:2.794 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL宽度:7.5 mm
Base Number Matches:1

IDT74LVCH162721APV8 数据手册

 浏览型号IDT74LVCH162721APV8的Datasheet PDF文件第2页浏览型号IDT74LVCH162721APV8的Datasheet PDF文件第3页浏览型号IDT74LVCH162721APV8的Datasheet PDF文件第4页浏览型号IDT74LVCH162721APV8的Datasheet PDF文件第5页浏览型号IDT74LVCH162721APV8的Datasheet PDF文件第6页 
IDT74LVCH162721A  
3.3V CMOS 20-BIT  
FLIP-FLOP WITH 3-STATE  
OUTPUTS, 5 VOLT TOLERANT I/O  
AND BUS-HOLD  
FEATURES:  
DESCRIPTION:  
• Typical tSK(o) (Output Skew) < 250ps  
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using  
machine model (C = 200pF, R = 0)  
This20-bitflip-flopisbuiltusingadvanceddualmetalCMOStechnology.  
The20flip-flopsoftheLVCH162721Aareedge-triggeredD-typeflip-flops  
with qualified clock storage. On the positive transition of the clock (CLK)  
input, the device provides true data at the Q outputs if the clock-enable  
(CLKEN) input is low. If CLKEN is high, no data is stored.  
• VCC = 3.3V ± 0.3V, Normal Range  
• VCC = 2.7V to 3.6V, Extended Range  
• CMOS power levels (0.4µ W typ. static)  
• All inputs, outputs, and I/O are 5V tolerant  
• Supports hot insertion  
A buffered output-enable (OE) input places the 20 outputs in either a  
normal logic state (high or low) or a high-impedance state. In the high-  
impedancestate,theoutputsneitherloadnordrivethebuslinessignificantly.  
The high-impedance state and increased drive provide the capability to  
drivebuslineswithouttheneedforinterfaceorpullupcomponents. OEdoes  
notaffecttheinternaloperationoftheflip-flops. Olddatacanberetainedor  
newdatacanbeenteredwhiletheoutputsareinthehigh-impedancestate.  
The LVCH162721A has series resistors in the device output structure  
which will significantly reduce line noise when used with light loads. This  
driver has been designed to drive ±12mA at the designated threshold  
levels.  
• Available in SSOP, TSSOP, and TVSOP packages  
DRIVE FEATURES:  
• Balanced Output Drivers: ±12mA  
• Low switching noise  
APPLICATIONS:  
The LVCH162721A has “bus-hold” which retains the inputs’ last state  
whenevertheinputgoestoahighimpedance.Thispreventsfloatinginputs  
and eliminates the need for pull-up/down resistors.  
• 5V and 3.3V mixed voltage systems  
• Data communication and telecommunication systems  
FUNCTIONALBLOCKDIAGRAM  
1
OE  
56  
CLK  
29  
CLKEN  
CE  
C1  
1D  
2
Q1  
55  
D1  
To 19 Other Channels  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
OCTOBER 1999  
1
© 1999 Integrated Device Technology, Inc.  
DSC-4940/1  

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