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IDT74LVC138ADC8 PDF预览

IDT74LVC138ADC8

更新时间: 2024-11-21 20:10:27
品牌 Logo 应用领域
艾迪悌 - IDT 驱动输入元件光电二极管逻辑集成电路
页数 文件大小 规格书
6页 78K
描述
Decoder/Driver, LVC/LCX/Z Series, Inverted Output, CMOS, PDSO16, SOIC-16

IDT74LVC138ADC8 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP,
针数:16Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.5其他特性:3 ENABLE INPUTS
系列:LVC/LCX/Z输入调节:SCHMITT TRIGGER
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
长度:9.9 mm逻辑集成电路类型:OTHER DECODER/DRIVER
湿度敏感等级:3功能数量:1
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):240传播延迟(tpd):7.9 ns
认证状态:Not Qualified座面最大高度:1.75 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:20宽度:3.9 mm
Base Number Matches:1

IDT74LVC138ADC8 数据手册

 浏览型号IDT74LVC138ADC8的Datasheet PDF文件第2页浏览型号IDT74LVC138ADC8的Datasheet PDF文件第3页浏览型号IDT74LVC138ADC8的Datasheet PDF文件第4页浏览型号IDT74LVC138ADC8的Datasheet PDF文件第5页浏览型号IDT74LVC138ADC8的Datasheet PDF文件第6页 
3.3V CMOS  
3-LINE TO 8-LINE  
IDT74LVC138A  
DECODER/DEMULTIPLEXER  
WITH 5 VOLT TOLERANT I/O  
FEATURES:  
DESCRIPTION:  
• 0.5 MICRON CMOS Technology  
The LVC138A 3-line to 8-line decoder/demultiplexer is built using  
advanced dual metal CMOS technology. This device is designed for high-  
performancememory-decodingordata-routingapplicationsrequiringvery  
shortpropagationdelaytimes. Inhighperformancememorysystems, this  
decoder minimizes the effects of system decoding. When employed with  
high-speedmemoriesutilizingafastenablecircuit,thedelaytimesofthese  
decodersandtheenabletimeofthememoryareusuallylessthanthetypical  
access time of the memory. This means that the effective system delay  
introduced by the decoder is negligible.  
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using  
machine model (C = 200pF, R = 0)  
• VCC = 3.3V ± 0.3V, Normal Range  
• VCC = 2.7V to 3.6V, Extended Range  
• CMOS power levels (0.4µ W typ. static)  
• Rail-to-Rail output swing for increased noise margin  
• All inputs, outputs, and I/Os are 5V tolerant  
• Supports hot insertion  
• Available in QSOP, SOIC, SSOP, and TSSOP packages  
The conditions at the binary-select inputs and the three enable inputs  
selectoneofeightoutputlines.Twoactive-lowenableinputsandoneactive-  
high enable input reduce the need for external gates or inverters when  
expanding. A24-linedecodercanbeimplementedwithoutexternalinvert-  
ers and a 32-line decoder requires only one inverter. An enable input can  
be used as a data input for demultiplexing applications.  
DRIVE FEATURES:  
• High Output Drivers: ±24mA  
• Reduced system switching noise  
Inputs can be driven from either 3.3V or 5V devices. This feature allows  
the use of this device as a translator in a mixed 3.3V/5V supply system.  
The LVC138A has been designed with a ±24mA output driver. This  
driver is capable of driving a moderate to heavy load while maintaining  
speedperformance.  
APPLICATIONS:  
• 5V and 3.3V mixed voltage systems  
• Data communication and telecommunication systems  
FUNCTIONALBLOCKDIAGRAM  
15  
Y0  
1
A
14  
Y1  
Select  
Inputs  
2
13  
B
Y2  
3
12  
Y3  
C
Data  
Outputs  
11  
Y4  
10  
Y5  
9
Y6  
6
G1  
7
Y7  
4
Enable  
G2A  
Inputs  
5
G2B  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
AUGUST 1999  
1
©1999 Integrated Device Technology, Inc.  
DSC-4722/1  

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