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IDT74FCT833BPQ PDF预览

IDT74FCT833BPQ

更新时间: 2024-11-23 12:59:03
品牌 Logo 应用领域
艾迪悌 - IDT 总线收发器
页数 文件大小 规格书
8页 75K
描述
Registered Bus Transceiver, 1-Func, 8-Bit, True Output, CMOS, PDIP24

IDT74FCT833BPQ 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete包装说明:DIP, DIP24,.3
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.92控制类型:INDEPENDENT CONTROL
计数方向:BIDIRECTIONALJESD-30 代码:R-PDIP-T24
JESD-609代码:e0逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
最大I(ol):0.048 A位数:8
功能数量:1端子数量:24
最高工作温度:70 °C最低工作温度:
输出特性:OPEN-DRAIN/3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP24,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):225
电源:5 VProp。Delay @ Nom-Sup:10.5 ns
子类别:Bus Driver/Transceivers标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
翻译:N/A触发器类型:POSITIVE EDGE
Base Number Matches:1

IDT74FCT833BPQ 数据手册

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IDT54/74FCT833A  
IDT54/74FCT833B  
FAST CMOS  
PARITY BUS  
TRANSCEIVER  
Integrated Device Technology, Inc.  
FEATURES:  
DESCRIPTION:  
• Equivalent to AMD’s Am29833 bipolar parity bus  
transceiver in pinout/function, speed and output drive  
over full temperature and voltage supply extremes  
• High-speed bidirectional bus transceiver for processor-  
organized devices  
The IDT54/74FCT833s are high-performance bus  
transceivers designed for two-way communications. They  
eachcontainan8-bitdatapathfromtheR(port)totheT(port),  
an 8-bit data path from the T (port) to the R (port), and a 9-bit  
parity checker/generator. The error flag can be clocked and  
stored in a register and read at the ERR output. The clear  
(CLR) input is used to clear the error flag register.  
• IDT54/74FCT833A equivalent to Am29833A speed and  
output drive  
• IDT54/74FCT833B 30% faster than Am29833A  
• Buffered direction and three-state controls  
• Error flag with open-drain output  
• IOL = 48mA (commercial) and 32mA (military)  
• TTL input and output level compatible  
• CMOS output level compatible  
The output enables OET and OER are used to force the  
port outputs to the high-impedance state so that the device  
can drive bus lines directly. In addition, OER and OET can be  
used to force a parity error by enabling both lines  
simultaneously. This transmission of inverted parity gives the  
designer more system diagnostic capability. The devices are  
specified at 48mA and 32mA output sink current over the  
commercial and military temperature ranges, respectively.  
• Substantially lower input current levels than AMD’s  
bipolar Am29800 series (5µA max.)  
• Available in plastic DIP, CERDIP, LCC and SOIC  
• Product available in Radiation Tolerant and Radiation  
Enhanced versions  
• Military product compliant to MIL-STD-883, Class B  
FUNCTIONAL BLOCK DIAGRAM  
R
I
T
I
8
8
PARITY  
T
OE  
OE  
R
8
8
S
MUX  
9
9-BIT  
PARITY TREE  
D
Q
Q
ERR  
P
CP  
CLR  
CLK  
CLR  
2557 drw 01  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
MAY 1992  
1992 Integrated Device Technology, Inc.  
7.21  
DSC-4621/2  
1

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