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IDT74FCT162652ATPV PDF预览

IDT74FCT162652ATPV

更新时间： 2024-10-28 23:12:47
品牌 Logo 应用领域
艾迪悌 - IDT 总线驱动器总线收发器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
9页 184K
描述
FAST CMOS 16-BIT BUS TRANSCEIVER/ REGISTERS

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中文翻译

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IDT74FCT162652ATPV 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：SSOP包装说明：SSOP-56
针数：56Reach Compliance Code：not_compliant
风险等级：5.28Is Samacsys：N
其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION控制类型：INDEPENDENT CONTROL
计数方向：BIDIRECTIONAL系列：FCT
JESD-30 代码：R-PDSO-G56JESD-609代码：e0
长度：18.415 mm负载电容（CL）：50 pF
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER最大I（ol）：0.024 A
湿度敏感等级：1位数：8
功能数量：2端口数量：2
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE WITH SERIES RESISTOR
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装等效代码：SSOP56,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
Prop。Delay @ Nom-Sup：6.3 ns传播延迟（tpd）：6.3 ns
认证状态：Not Qualified座面最大高度：2.794 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn85Pb15)
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A触发器类型：POSITIVE EDGE
宽度：7.5 mmBase Number Matches：1

IDT74FCT162652ATPV 数据手册

 浏览型号IDT74FCT162652ATPV的Datasheet PDF文件第2页浏览型号IDT74FCT162652ATPV的Datasheet PDF文件第3页浏览型号IDT74FCT162652ATPV的Datasheet PDF文件第4页浏览型号IDT74FCT162652ATPV的Datasheet PDF文件第5页浏览型号IDT74FCT162652ATPV的Datasheet PDF文件第6页浏览型号IDT74FCT162652ATPV的Datasheet PDF文件第7页 
IDT54/74FCT16652T/AT/CT/ET  
IDT54/74FCT162652T/AT/CT/ET  
FAST CMOS 16-BIT BUS  
TRANSCEIVER/  
REGISTERS  
Integrated Device Technology, Inc.  
vicesareorganizedastwoindependent8-bitbustransceivers  
with 3-state D-type registers. For example, the xOEAB and  
xOEBA signals control the transceiver functions.  
The xSAB and xSBA control pins are provided to select  
either real time or stored data transfer. The circuitry used for  
select control will eliminate the typical decoding glitch that  
occurs in a multiplexer during the transition between stored  
and real time data. A LOW input level selects real-time data  
and a HIGH level selects stored data.  
Data on the A or B data bus, or both, can be stored in the  
internal D-flip-flops by LOW-to-HIGH transitions at the appro-  
priate clock pins (xCLKAB or xCLKBA), regardless of the  
select or enable control pins. Flow-through organization of  
signal pins simplifies layout. All inputs are designed with  
hysteresis for improved noise margin.  
The FCT16652T/AT/CT/ET are ideally suited for driving  
high capacitance loads and low-impedance backplanes. The  
output buffers are designed with power off disable capability  
to allow "live insertion" of boards when used as backplane  
drivers.  
FEATURES:  
• Common features:  
– 0.5 MICRON CMOS Technology  
– High-speed, low-power CMOS replacement for  
ABT functions  
– Typical tSK(o) (Output Skew) < 250ps  
– Low input and output leakage ≤1µA (max.)  
– ESD > 2000V per MIL-STD-883, Method 3015;  
> 200V using machine model (C = 200pF, R = 0)  
– Packages include 25 mil pitch SSOP, 19.6 mil pitch  
TSSOP,15.7 mil pitch TVSOP and 25 mil pitch Cerpack  
– Extended commercial range of -40°C to +85°C  
– VCC = 5V ±10%  
• Features for FCT16652T/AT/CT/ET:  
– High drive outputs (-32mA IOH, 64mA IOL)  
– Power off disable outputs permit “live insertion”  
– Typical VOLP (Output Ground Bounce) < 1.0V at  
VCC = 5V, TA = 25°C  
• Features for FCT162652T/AT/CT/ET:  
– Balanced Output Drivers: ±24mA (commercial),  
±16mA (military)  
– Reduced system switching noise  
– Typical VOLP (Output Ground Bounce) < 0.6V at  
VCC = 5V,TA = 25°C  
The FCT162652T/AT/CT/ET have balanced output drive  
with current limiting resistors. This offers low ground bounce,  
minimalundershoot,andcontrolledoutputfalltimes–reducing  
the need for external series terminating resistors. The  
FCT162652T/AT/CT/ET are plug-in replacements for the  
FCT16652T/AT/CT/ETandABT16652foron-boardbusinter-  
face applications.  
DESCRIPTION:  
The FCT16652T/AT/CT/ET and FCT162652T/AT/CT/ET  
16-bit registered transceivers are built using advanced dual  
metal CMOS technology. These high-speed, low-power de-  
FUNCTIONAL BLOCK DIAGRAM  
2OEAB  
1
OEAB  
OEBA  
CLKBA  
SBA  
CLKAB  
2OEBA  
2CLKBA  
1
1
1
1
2SBA  
2CLKAB  
2SAB  
1
SAB  
B REG  
B REG  
D
D
C
C
2B1  
1B1  
A REG  
A REG  
2A1  
1A1  
D
D
C
C
TO 7 OTHER CHANNELS  
TO 7 OTHER CHANNELS  
2549 drw 02  
2549 drw 01  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
MILITARY AND COMMERCIAL TEMPERATURE RANGE  
AUGUST 1996  
1996 Integrated Device Technology, Inc.  
DSC-2549/8  
1
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