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IDT74ALVCHR162269APV8 PDF预览

IDT74ALVCHR162269APV8

更新时间: 2024-11-07 10:44:43
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管逻辑集成电路
页数 文件大小 规格书
7页 80K
描述
Bus Exchanger, ALVC/VCX/A Series, 1-Func, 12-Bit, True Output, CMOS, PDSO56, 0.635 MM PITCH, SSOP-56

IDT74ALVCHR162269APV8 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SSOP包装说明:SSOP,
针数:56Reach Compliance Code:compliant
风险等级:5.63其他特性:WITH SYNCHRONOUS O/P ENABLES AND MUX SELECT
系列:ALVC/VCX/AJESD-30 代码:R-PDSO-G56
长度:18.415 mm逻辑集成电路类型:BUS EXCHANGER
位数:12功能数量:1
端口数量:3端子数量:56
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE WITH SERIES RESISTOR输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):6.9 ns
认证状态:Not Qualified座面最大高度:2.794 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mm

IDT74ALVCHR162269APV8 数据手册

 浏览型号IDT74ALVCHR162269APV8的Datasheet PDF文件第2页浏览型号IDT74ALVCHR162269APV8的Datasheet PDF文件第3页浏览型号IDT74ALVCHR162269APV8的Datasheet PDF文件第4页浏览型号IDT74ALVCHR162269APV8的Datasheet PDF文件第5页浏览型号IDT74ALVCHR162269APV8的Datasheet PDF文件第6页浏览型号IDT74ALVCHR162269APV8的Datasheet PDF文件第7页 
3.3V CMOS 12-BIT TO  
IDT74ALVCHR162269A  
24-BIT REGISTERED BUS  
EXCHANGER WITH 3-STATE  
OUTPUTS AND BUS-HOLD  
DESCRIPTION:  
FEATURES:  
This12-bitto24-bitregisteredbusexchangerisusedinapplicationsin  
whichtwoseparateportsmustbemultiplexedonto,ordemultiplexedfrom,  
asingleport.Itisparticularlysuitableasaninterfacebetweensynchronous  
DRAMs and high-speed microprocessors.  
• 0.5 MICRON CMOS Technology  
• Typical tSK(o) (Output Skew) < 250ps  
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using  
machine model (C = 200pF, R = 0)  
DataisstoredintheinternalB-portregistersonthelow-to-hightransition  
of the clock (CLK) input when the appropriate clock-enable (CLKENA)  
inputsarelow. Propercontroloftheseinputsallowstwosequential12-bit  
words to be presented as a 24-bit word on the B-port. For data transfer  
intheB-to-Adirection,asinglestorageregisterisprovided.TheselectSEL  
line selects 1B or 2B data for the A outputs. The register on the A output  
permitsthefastestpossibledatatransfer,thusextendingtheperiodduring  
which the data is valid on the bus. The control terminals are registered so  
thatalltransactionsaresynchronouswithCLK. Dataflowiscontrolledby  
the active-low output enables (OEA, OEB1 and OEB2).  
• VCC = 3.3V ± 0.3V, Normal Range  
• VCC = 2.7V to 3.6V, Extended Range  
• VCC = 2.5V ± 0.2V  
• CMOS power levels (0.4µ W typ. static)  
• Rail-to-Rail output swing for increased noise margin  
• Available in SSOP, TSSOP, and TVSOP packages  
DRIVE FEATURES:  
• Balanced Output Drivers: ±12mA  
• Low Switching Noise  
The ALVCHR162269A has series resistors in the device output struc-  
ture which will significantly reduce line noise when used with light loads.  
Thisdriverhasbeendesignedtodrive±12mAatthedesignatedthreshold  
levels.  
TheALVCHR162269Ahasbus-holdwhichretainstheinputslaststate  
whenevertheinputgoestoahighimpedance.Thispreventsfloatinginputs  
and eliminates the need for pull-up/down resistors.  
APPLICATIONS:  
• 3.3V high speed systems  
• 3.3V and lower voltage computing systems  
FUNCTIONALBLOCKDIAGRAM  
29  
CLK  
C1  
1D  
2
OEB1  
C1  
1D  
56  
OEB2  
30  
CLKENA1  
55  
CLKENA2  
C1  
1D  
28  
SEL  
1
OEA  
1D  
C1  
1 of 12 Channels  
C1  
8
23  
1B1  
A1  
0
1
1D  
CE  
C1  
1D  
6
2B1  
CE  
C1  
1D  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
MARCH 1999  
1
© 1999 Integrated Device Technology, Inc.  
DSC-4239/1  

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