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IDT74ALVCH374PG

更新时间： 2024-09-16 04:58:31
品牌 Logo 应用领域
艾迪悌 - IDT 触发器输出元件
页数 文件大小 规格书
6页 84K
描述
3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS AND BUS-HOLD

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中文翻译

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IDT74ALVCH374PG 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP, TSSOP20,.25
针数：20Reach Compliance Code：not_compliant
风险等级：5.63系列：ALVC/VCX/A
JESD-30 代码：R-PDSO-G20JESD-609代码：e0
长度：6.5 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.024 A
湿度敏感等级：1位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP20,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源：3.3 VProp。Delay @ Nom-Sup：6 ns
传播延迟（tpd）：7 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：FF/Latches
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn85Pb15)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
触发器类型：POSITIVE EDGE宽度：4.4 mm
Base Number Matches：1

IDT74ALVCH374PG 数据手册

 浏览型号IDT74ALVCH374PG的Datasheet PDF文件第2页浏览型号IDT74ALVCH374PG的Datasheet PDF文件第3页浏览型号IDT74ALVCH374PG的Datasheet PDF文件第4页浏览型号IDT74ALVCH374PG的Datasheet PDF文件第5页浏览型号IDT74ALVCH374PG的Datasheet PDF文件第6页 
3.3V CMOS OCTAL POSITIVE  
EDGE-TRIGGERED D-TYPE  
IDT74ALVCH374  
ADVANCE  
FLIP-FLOP WITH 3-STATE  
INFORMATION  
OUTPUTS AND BUS-HOLD  
FEATURES:  
DESCRIPTION:  
–
–
–
0.5 MICRON CMOS Technology  
Thisoctalpostiveedge-triggeredD-typeflip-flopisbuiltusingadvanced  
dual metal CMOS technology. The ALVCH374 device is particularly  
suitable for implementing buffer registers, I/O ports, bidirectional bus  
drivers,andworkingregisters.Onthepositivetransitionoftheclock(CLK)  
input, the Qoutputs are settothe logiclevels atthe data (D)inputs.  
TypicaltSK(o) (Output Skew) < 250ps  
ESD > 2000V per MIL-STD-883, Method 3015;  
> 200V using machine model (C = 200pF, R = 0)  
1.27mm pitch SOIC, 0.65mm pitch SSOP,  
0.635mm pitch QSOP, 0.65mm TSSOP packages  
Extended commercial range of -40°C to +85°C  
VCC = 3.3V ±0.3V, Normal Range  
VCC = 2.7V to 3.6V, Extended Range  
VCC = 2.5V ±0.2V  
CMOS power levels (0.4µW typ. static)  
Rail-to-Rail output swing for increased noise margin  
–
–
–
–
–
–
–
A buffered output-enable (OE) input can be used to place the eight  
outputs in either a normal logic state (high or low logic levels) or a high-  
impedancestate.Inthehigh-impedancestate,theoutputsneitherloadnor  
drivethebuslinessignificantly.Thehigh-impedancestateandincreased  
drive provide the capability to drive bus lines without interface or pullup  
components. OEdoes notaffectinternaloperations ofthelatch.Olddata  
can be retained or new data can be entered while the outputs are in the  
high-impedancestate.  
Drive Features for ALVCH374:  
–
–
High Output Drivers: ±24mA  
Suitable for heavy loads  
The ALVCH374has beendesignedwitha ±24mAoutputdriver. This  
driver is capable of driving a moderate to heavy load while maintaining  
speedperformance.  
APPLICATIONS:  
• 3.3V High Speed Systems  
• 3.3Vandlowervoltagecomputingsystems  
The ALVCH374 has a “bus-hold” which retains the inputs’ last state  
wheneverthe inputbus goes toa highimpedance.This prevents floating  
inputs andeliminates the needforpull-up/downresistors.  
Functional Block Diagram  
1
OE  
11  
CLK  
C1  
1D  
2
1Q  
3
1D  
TO SEVEN OTHER CHANNELS  
EXTENDED COMMERCIAL TEMPERATURE RANGE  
MARCH1999  
1
c
1999 Integrated Device Technology, Inc.  
DSC-4473/-  
123456

中文翻译

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IDT74ALVCH374PG 替代型号

型号 品牌 替代类型 描述 数据表
SN74ALVCH374PW TI

功能相似

 OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

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