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IDT74ALVCH32244 PDF预览

IDT74ALVCH32244

更新时间: 2024-11-22 22:36:07
品牌 Logo 应用领域
艾迪悌 - IDT 驱动器输出元件
页数 文件大小 规格书
7页 118K
描述
3.3V CMOS 32-BIT BUFFER/ DRIVER WITH 3-STATE OUTPUTS AND BUS-HOLD

IDT74ALVCH32244 数据手册

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3.3V CMOS 32-BIT  
IDT74ALVCH32244  
BUFFER/ DRIVER WITH  
3-STATE OUTPUTS AND  
BUS-HOLD  
DESCRIPTION:  
FEATURES:  
This 32-bit buffer/driver is built using advanced dual metal CMOS  
technology. This high-speed, low power device offers bus/backplane  
interface capability with improved packing density. The device has a flow-  
throughorganizationforsimplifyingboardlayout. Thethree-statecontrols  
operatethisdeviceinaQuad-Nibble,Dual-Byteorsingle16-bitwordmode.  
All inputs are designed with hysteresis for improved noise margin.  
The ALVCH32244 has been designed with a ±24mA output driver. This  
driver is capable of driving a moderate to heavy load while maintaining  
speedperformance.  
• 0.5 MICRON CMOS Technology  
• Typical tSK(o) (Output Skew) < 250ps  
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using  
machine model (C = 200pF, R = 0)  
• VCC = 3.3V ± 0.3V, Normal Range  
• VCC = 2.7V to 3.6V, Extended Range  
• VCC = 2.5V ± 0.2V  
• CMOS power levels (0.4µ W typ. static)  
• Rail-to-Rail output swing for increased noise margin  
• Available in 96-ball LFBGA package  
The ALVCH32244 has “bus-hold” which retains the inputs’ last state  
whenever the input bus goes to a high impedance. This prevents floating  
inputs and eliminates the need for pull-up/down resistors.  
DRIVE FEATURES:  
• High Output Drivers: ±24mA  
• Suitable for Heavy Loads  
APPLICATIONS:  
• 3.3V high speed systems  
• 3.3V and lower voltage computing systems  
FUNCTIONALBLOCKDIAGRAM  
J3  
J5  
A3  
A5  
H4  
E5  
T4  
N5  
3OE  
7OE  
1OE  
1A1  
5OE  
5A1  
5A2  
5A3  
5A4  
A2  
E2  
J2  
N2  
1Y1  
1Y2  
1Y3  
1Y4  
3Y1  
5Y1  
7Y1  
3A1  
3A2  
7A1  
7A2  
A1  
B2  
A6  
B5  
B6  
J1  
N6  
P5  
N1  
P2  
P1  
E6  
F5  
F6  
E1  
F2  
J6  
5Y2  
5Y3  
5Y4  
1A2  
3Y2  
3Y3  
7Y2  
7Y3  
K2  
K1  
K5  
K6  
1A3  
1A4  
3A3  
3A4  
7A3  
7A4  
B1  
F1  
P6  
3Y4  
7Y4  
A4  
J4  
L5  
T3  
H3  
2OE  
6OE  
4OE  
8OE  
C5  
C6  
D5  
D6  
L2  
C2  
C1  
D2  
D1  
G2  
G1  
H1  
H2  
R5  
R6  
T6  
T5  
R2  
R1  
T1  
T2  
G5  
G6  
H6  
H5  
2Y1  
6Y1  
4Y1  
8Y1  
2A1  
2A2  
6A1  
6A2  
4A1  
4A2  
8A1  
8A2  
L6  
L1  
2Y2  
2Y3  
6Y2  
6Y3  
4Y2  
4Y3  
8Y2  
8Y3  
M2  
M5  
M6  
2A3  
2A4  
6A3  
6A4  
4A3  
4A4  
8A3  
8A4  
M1  
2Y4  
6Y4  
4Y4  
8Y4  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
FEBRUARY 2000  
1
©2000 Integrated Device Technology, Inc.  
DSC-4906/1  

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