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IDT74ALVCH162374PV8 PDF预览

IDT74ALVCH162374PV8

更新时间: 2024-02-04 10:14:43
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
6页 104K
描述
Bus Driver, ALVC/VCX/A Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, 0.635 MM PITCH, SSOP-48

IDT74ALVCH162374PV8 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SSOP包装说明:SSOP,
针数:48Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.61
系列:ALVC/VCX/AJESD-30 代码:R-PDSO-G48
长度:15.875 mm逻辑集成电路类型:BUS DRIVER
位数:8功能数量:2
端口数量:2端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE WITH SERIES RESISTOR输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):5.4 ns
认证状态:Not Qualified座面最大高度:2.794 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mmBase Number Matches:1

IDT74ALVCH162374PV8 数据手册

 浏览型号IDT74ALVCH162374PV8的Datasheet PDF文件第2页浏览型号IDT74ALVCH162374PV8的Datasheet PDF文件第3页浏览型号IDT74ALVCH162374PV8的Datasheet PDF文件第4页浏览型号IDT74ALVCH162374PV8的Datasheet PDF文件第5页浏览型号IDT74ALVCH162374PV8的Datasheet PDF文件第6页 
3.3V CMOS 16-BIT EDGE-  
TRIGGERED D-TYPE FLIP-  
IDT74ALVCH162374  
FLOP WITH 3-STATE OUT-  
PUTS AND BUS-HOLD  
DESCRIPTION:  
FEATURES:  
0.5 MICRON CMOS Technology  
TypicaltSK(0) (Output Skew) < 250ps  
This 16-bit edge-triggered D-type flip-flop is built using advanced dual  
metal CMOS technology. The ALVCH162374 is particularly suitable for  
implementing buffer registers, I/O ports, bidirectional bus drivers, and  
working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-  
flop. On the positive transition of the clock (CLK) input, the Q outputs of  
the flip-flop take on the logic levels set up at the data (D) inputs. OE can  
be used to place the eight outputs in either a normal logic state (high or  
low logic levels) or a high-impedance state. In the high-impedance  
state, the outputs neither load nor drive the bus lines significantly. The  
high-impedance state and the increased drive provide the capability to  
drive bus lines without need for interface or pullup components. OE does  
not affect internal operations of the flip-flop. Old data can be retained or  
new data can be entered while the outputs are in the high-impedance  
state.  
ESD > 2000V per MIL-STD-883, Method 3015;  
> 200V using machine model (C = 200pF, R = 0)  
0.635mm pitch SSOP, 0.50mm pitch TSSOP,  
and 0.40mm pitch TVSOP packages  
Extended commercial range of – 40°C to + 85°C  
VCC = 3.3V ± 0.3V, Normal Range  
VCC = 2.7V to 3.6V, Extended Range  
VCC = 2.5V ± 0.2V  
CMOS power levels (0.4µW typ. static)  
Rail-to-Rail output swing for increased noise margin  
Drive Features for ALVCH162374:  
Balanced Output Drivers: ±12mA  
Low switching noise  
The ALVCH162374 has series resistors in the device output structure  
which will significantly reduce line noise when used with light loads. This  
driver has been designed to drive ±12mA at the designated threshold  
levels.  
APPLICATIONS:  
3.3V High Speed Systems  
3.3V and lower voltage computing systems  
The ALVCH162374 has bus-hold” which retains the inputs’ last state  
whenever the input goes to a high impedance. This prevents floating  
inputs and eliminates the need for pull-up/down resistor.  
Functional Block Diagram  
1
24  
2OE  
1OE  
48  
25  
2CLK  
1CLK  
C1  
C1  
2
13  
1Q1  
2Q1  
47  
36  
1D1  
1D  
1D  
2D1  
TO 7 OTHER CHANNELS  
TO 7 OTHER CHANNELS  
EXTENDED COMMERCIAL TEMPERATURE RANGE  
MARCH1999  
1
c
1999 Integrated Device Technology, Inc.  
DSC-4565/-  

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