Datasheet > IDT74ALVC10DC

IDT74ALVC10DC

更新时间： 2024-09-22 23:58:19

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描述
Triple 3-input NAND Gate

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IDT74ALVC10DC 数据手册

IDT74ALVC10

3.3VCMOSTRIPLE3-INPUTPOSITIVE-NANDGATE

INDUSTRIALTEMPERATURERANGE

IDT74ALVC10

3.3V CMOS

TRIPLE 3-INPUT

POSITIVE-NAND GATE

DESCRIPTION:

FEATURES:

Thistriple3-inputpositive-NANDgateisbuiltusingadvanceddualmetal

CMOS technology. The ALVC10 performs the Boolean function

Y = A • B • C or Y = A + B + C in positive logic.

–

0.5 MICRON CMOS Technology

ESD > 2000V per MIL-STD-883, Method 3015;

> 200V using machine model (C = 200pF, R = 0)

V^CC= 3.3V ± 0.3V, Normal Range

V^CC= 2.7V to 3.6V, Extended Range

V^CC= 2.5V ± 0.2V

CMOS power levels (0.4µW typ. static)

Rail-to-Rail output swing for increased noise margin

Available in SOIC, SSOP and TSSOP packages

–

TheALVC10hasbeendesignedwitha±24mAoutputdriver. Thisdriver

is capable of driving a moderate to heavy load while maintaining speed

performance.

APPLICATIONS:

Drive Features for ALVC10:

–

• 3.3V High Speed Systems

• 3.3V and lower voltage computing systems

High Output Drivers: ±24mA

Suitable forheavyloads

FUNCTIONALBLOCKDIAGRAM

PIN CONFIGURATION

¹A

¹B

²A

²B

V^CC

¹C

¹Y

³C

³B

³A

³Y

SO14-1

SO14-2

SO14-3

²C

²Y

GND

SOIC/ SSOP/ TSSOP

TOP VIEW

(1)

FUNCTION TABLE (each gate)

PIN DESCRIPTION

Inputs

Output

Pin Names

Description

xA, xB, xC

Data Inputs

Data Outputs

NOTE:

1. H = HIGH Voltage Level

L = LOW Voltage Level

X = Don't Care

INDUSTRIAL TEMPERATURE RANGE

JUNE 2000

1999 Integrated Device Technology, Inc.

DSC-4634/-

12 3 4 5

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