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IDT72P51569L6BBGI PDF预览

IDT72P51569L6BBGI

更新时间: 2024-11-26 15:43:07
品牌 Logo 应用领域
艾迪悌 - IDT 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
87页 830K
描述
FIFO, 128KX36, 3.7ns, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-256

IDT72P51569L6BBGI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:BGA
包装说明:BGA, BGA256,16X16,40针数:256
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.84
最长访问时间:3.7 ns最大时钟频率 (fCLK):166 MHz
周期时间:6 nsJESD-30 代码:S-PBGA-B256
JESD-609代码:e1长度:17 mm
内存密度:4718592 bit内存集成电路类型:OTHER FIFO
内存宽度:36湿度敏感等级:3
功能数量:1端子数量:256
字数:131072 words字数代码:128000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:128KX36
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA256,16X16,40
封装形状:SQUARE封装形式:GRID ARRAY
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:1.8 V认证状态:Not Qualified
座面最大高度:3.5 mm最大待机电流:0.1 A
子类别:FIFOs最大压摆率:0.15 mA
最大供电电压 (Vsup):1.9 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30宽度:17 mm
Base Number Matches:1

IDT72P51569L6BBGI 数据手册

 浏览型号IDT72P51569L6BBGI的Datasheet PDF文件第2页浏览型号IDT72P51569L6BBGI的Datasheet PDF文件第3页浏览型号IDT72P51569L6BBGI的Datasheet PDF文件第4页浏览型号IDT72P51569L6BBGI的Datasheet PDF文件第5页浏览型号IDT72P51569L6BBGI的Datasheet PDF文件第6页浏览型号IDT72P51569L6BBGI的Datasheet PDF文件第7页 
1.8VMULTI-QUEUEFLOW-CONTROLDEVICES  
(32QUEUES)36BITWIDECONFIGURATION  
589,824bits  
1,179,648bits  
2,359,296bits  
IDT72P51539  
IDT72P51549  
IDT72P51559  
IDT72P51569  
4,718,592bits  
User Selectable Bus Matching Options:  
FEATURES  
– x36 in to x36 out  
– x36in to x18out  
– x36in to x9out  
– x18 in to x36 out  
– x18 in to x18 out  
– x18 in to x9 out  
– x9 in to x36 out  
– x9 in to x18 out  
– x9 in to x9 out  
Choose from among the following memory density options:  
IDT72P51539  
IDT72P51549  
IDT72P51559  
IDT72P51569  
Total Available Memory = 589,824 bits  
Total Available Memory = 1,179,648 bits  
Total Available Memory = 2,359,296 bits  
Total Available Memory = 4,718,592 bits  
User selectable I/O: 1.5V HSTL, 1.8V eHSTL, or 2.5V LVTTL  
100% Bus Utilization, Read and Write on every clock cycle  
Selectable First Word Fall Through (FWFT) or IDT standard  
mode of operation  
Ability to operate on packet or word boundaries  
Mark and Re-Write operation  
Configurable from 1 to 32 Queues  
Default configuration of 32 or 16 symmetrical queues  
Default multi-queue device configurations  
IDT72P51539: 512 x 36 x 32Q  
Mark and Re-Read operation  
IDT72P51549: 1,024 x 36 x 32Q  
IDT72P51559: 2,048 x 36 x 32Q  
IDT72P51569: 4,096 x 36 x 32Q  
Individual, Active queue flags (OR / EF, IR / FF, PAE, PAF, PR)  
8 bit parallel flag status on both read and write ports  
Direct or polled operation of flag status bus  
Expansion of up to 256 queues and/or 32Mb logical configura-  
tion using up to 8 multi-queue devices in parallel  
JTAG Functionality (Boundary Scan)  
Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm  
HIGH Performance submicron CMOS technology  
Industrial temperature range (-40°C to +85°C) is available  
Green parts available, see Ordering Information  
Default configuration can be augmented via the queue address  
bus  
Number of queues and individual queue sizes may be  
configured at master reset though serial programming  
200 MHz High speed operation (5ns cycle time)  
3.6ns access time  
Independent Read and Write access per queue  
FUNCTIONALBLOCKDIAGRAM  
MULTI-QUEUE FLOW-CONTROL DEVICE  
RADEN  
ESTR  
Q31  
WADEN  
FSTR  
RDADD  
WRADD  
8
8
REN  
RCLK  
RCS  
WEN  
Q30  
Q29  
WCLK  
WCS  
OE  
Q
out  
x36, x18 or x9  
DATA OUT  
D
in  
x36, 18 or x9  
DATA IN  
EF/OR  
FF/IR  
PAF  
PR  
PAE  
Q0  
PAFn  
PAEn  
PRn  
8
8
6715 drw01  
CIDTOandMtheMIDTElogRoaCretrIaAdemLarksAofInNtegDratedIDNevicDeTUechSnolTogyR,InIcAL TEMPERATURE RANGES  
AUGUST 2005  
1
2005 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-6715/3  

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