256K X 36, 512K X 18
3.3VSynchronousSRAMs
2.5V I/O, Burst Counter
IDT71V67702
IDT71V67902
Flow-ThroughOutputs,SingleCycleDeselect
Features
◆
data, address and control registers. There are no registers in the data
outputpath(flow-througharchitecture). InternallogicallowstheSRAMto
generateaself-timedwritebaseduponadecisionwhichcanbeleftuntil
theendofthewritecycle.
Theburstmodefeatureoffersthehighestlevelofperformancetothe
systemdesigner,astheIDT71V67702/7902canprovidefourcyclesof
dataforasingleaddresspresentedtotheSRAM. Aninternalburstaddress
counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe
accesssequence.Thefirstcycleofoutputdatawillflow-throughfromthe
arrayafteraclock-to-dataaccesstimedelayfromtherisingclockedgeof
256K x 36, 512K x 18 memory configurations
◆
Supports fast access times:
– 7.5ns up to 117MHz clock frequency
– 8.0ns up to 100MHz clock frequency
– 8.5ns up to 87MHz clock frequency
input selects interleaved or linear burst mode
Self-timedwritecyclewithglobalwritecontrol( ),bytewrite
◆
◆
enable (
3.3V core power supply
Power down controlled by ZZ input
2.5V I/O supply (VDDQ)
Packaged in a JEDEC Standard 100-pin thin plastic quad
flatpack(TQFP),119ballgridarray(BGA)and165finepitchball
grid array (fBGA).
), and byte writes ( x)
◆
◆
◆
◆
the same cycle. If burst mode operation is selected (
=LOW), the
subsequentthreecyclesofoutputdatawillbeavailabletotheuseronthe
next three rising clock edges. The order of these three addresses are
definedbytheinternalburstcounterandthe
inputpin.
TheIDT71V67702/7902SRAMsutilizeIDT’slatesthigh-performance
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm
100-pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray
(BGA) and a 165 fine pitch ball grid array (fBGA).
Description
The IDT71V67702/7902 are high-speed SRAMs organized as
256Kx36/512Kx18.TheIDT71V67702/7902SRAMs containwrite,
PinDescriptionSummary
A0-A18
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Chip Enable
CE
CS0, CS1
OE
Chip Selects
Output Enable
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
GW
BWE
(1)
BW1, BW2, BW3, BW4
CLK
Clock
Input
Input
Input
Input
Input
Input
I/O
N/A
Synchronous
Synchronous
Synchronous
DC
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Linear / Interleaved Burst Order
Sleep Mode
ADV
ADSC
ADSP
LBO
ZZ
Asynchronous
Synchronous
N/A
I/O0-I/O31, I/OP1-I/OP4
Data Input / Output
VDD, VDDQ
VSS
Core Power, I/O Power
Ground
Supply
Supply
N/A
5317 tbl 01
NOTE:
1.
3 and
4 are not applicable for the IDT71V67902.
DECEMBER 2003
1
©2002IntegratedDeviceTechnology,Inc.
DSC-5317/08