Datasheet > 存储 > SRAM> IDT71V67702S75BQI

IDT71V67702S75BQI

更新时间： 2024-02-07 23:42:26

品牌	Logo	应用领域
艾迪悌 - IDT		计数器静态存储器
页数	文件大小	规格书
23页	514K
描述
256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect

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256K X 36, 512K X 18

3.3VSynchronousSRAMs

2.5V I/O, Burst Counter

IDT71V67702

IDT71V67902

Flow-ThroughOutputs,SingleCycleDeselect

Features

◆

data, address and control registers. There are no registers in the data

outputpath(flow-througharchitecture). InternallogicallowstheSRAMto

generateaself-timedwritebaseduponadecisionwhichcanbeleftuntil

theendofthewritecycle.

Theburstmodefeatureoffersthehighestlevelofperformancetothe

systemdesigner,astheIDT71V67702/7902canprovidefourcyclesof

dataforasingleaddresspresentedtotheSRAM. Aninternalburstaddress

counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe

accesssequence.Thefirstcycleofoutputdatawillflow-throughfromthe

arrayafteraclock-to-dataaccesstimedelayfromtherisingclockedgeof

256K x 36, 512K x 18 memory configurations

◆

Supports fast access times:

– 7.5ns up to 117MHz clock frequency

– 8.0ns up to 100MHz clock frequency

– 8.5ns up to 87MHz clock frequency

input selects interleaved or linear burst mode

Self-timedwritecyclewithglobalwritecontrol( ),bytewrite

◆

enable (

3.3V core power supply

Power down controlled by ZZ input

2.5V I/O supply (VDDQ)

Packaged in a JEDEC Standard 100-pin thin plastic quad

flatpack(TQFP),119ballgridarray(BGA)and165finepitchball

grid array (fBGA).

), and byte writes ( x)

◆

the same cycle. If burst mode operation is selected (

=LOW), the

subsequentthreecyclesofoutputdatawillbeavailabletotheuseronthe

next three rising clock edges. The order of these three addresses are

definedbytheinternalburstcounterandthe

inputpin.

TheIDT71V67702/7902SRAMsutilizeIDT’slatesthigh-performance

CMOSprocessandarepackagedinaJEDECstandard14mmx20mm

100-pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray

(BGA) and a 165 fine pitch ball grid array (fBGA).

Description

The IDT71V67702/7902 are high-speed SRAMs organized as

256Kx36/512Kx18.TheIDT71V67702/7902SRAMs containwrite,

PinDescriptionSummary

A0-A18

Address Inputs

Input

Synchronous

Asynchronous

Synchronous

Chip Enable

CS0, CS1

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

BWE

(1)

BW1, BW2, BW3, BW4

CLK

Clock

Input

I/O

N/A

Synchronous

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Sleep Mode

ADV

ADSC

ADSP

LBO

Asynchronous

Synchronous

N/A

I/O0-I/O31, I/OP1-I/OP4

Data Input / Output

V_DD, V_DDQ

VSS

Core Power, I/O Power

Ground

Supply

N/A

5317 tbl 01

NOTE:

3 and

4 are not applicable for the IDT71V67902.

DECEMBER 2003

DSC-5317/08

12 3 4 5 6 7...23

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与IDT71V67702S75BQI相关器件

型号	品牌	获取价格	描述	数据表
IDT71V67702S75PF	IDT	获取价格	256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Flow-Through Outputs,
IDT71V67702S75PFI	IDT	获取价格	256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Flow-Through Outputs,
IDT71V67702S80BG	IDT	获取价格	256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Flow-Through Outputs,
IDT71V67702S80BGGI	IDT	获取价格	Cache SRAM, 256KX36, 8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V67702S80BGI	IDT	获取价格	256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Flow-Through Outputs,
IDT71V67702S80BGI8	IDT	获取价格	Cache SRAM, 256KX36, 8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V67702S80BQ	IDT	获取价格	256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Flow-Through Outputs,
IDT71V67702S80BQG	IDT	获取价格	Cache SRAM, 256KX36, 8ns, CMOS, PBGA165, 13 X 15 MM, FPBGA-165
IDT71V67702S80BQI	IDT	获取价格	256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Flow-Through Outputs,
IDT71V67702S80PF	IDT	获取价格	256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Flow-Through Outputs,

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