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IDT71V65903S85PFG

更新时间： 2024-11-08 13:08:43
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
26页 497K
描述
ZBT SRAM, 512KX18, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, GREEN, PLASTIC, MO-136DJ, TQFP-100

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IDT71V65903S85PFG 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFP
包装说明：LQFP, QFP100,.63X.87针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.33
最长访问时间：8.5 ns其他特性：FLOW-THROUGH ARCHITECTURE
最大时钟频率 (fCLK)：90 MHzI/O 类型：COMMON
JESD-30 代码：R-PQFP-G100JESD-609代码：e3
长度：20 mm内存密度：9437184 bit
内存集成电路类型：ZBT SRAM内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：100字数：524288 words
字数代码：512000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：512KX18输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP100,.63X.87封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified座面最大高度：1.6 mm
最大待机电流：0.04 A最小待机电流：3.14 V
子类别：SRAMs最大压摆率：0.225 mA
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Matte Tin (Sn) - annealed端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：14 mm
Base Number Matches：1

IDT71V65903S85PFG 数据手册

 浏览型号IDT71V65903S85PFG的Datasheet PDF文件第2页浏览型号IDT71V65903S85PFG的Datasheet PDF文件第3页浏览型号IDT71V65903S85PFG的Datasheet PDF文件第4页浏览型号IDT71V65903S85PFG的Datasheet PDF文件第5页浏览型号IDT71V65903S85PFG的Datasheet PDF文件第6页浏览型号IDT71V65903S85PFG的Datasheet PDF文件第7页 
256K x 36, 512K x 18  
IDT71V65703  
IDT71V65903  
3.3VSynchronousZBT™SRAMs  
3.3V I/O, Burst Counter  
Flow-Through Outputs  
cycle,andonthenextclockcycletheassociateddatacycleoccurs,beit  
read or write.  
TheIDT71V65703/5903containaddress,data-inandcontrolsignal  
registers.Theoutputsareflow-through(nooutputdataregister).Output  
enable is the only asynchronous signal and can be used to disable the  
outputsatanygiventime.  
Features  
◆
256K x 36, 512K x 18 memory configurations  
◆
Supports high performance system speed - 100 MHz  
(7.5 ns Clock-to-Data Access)  
ZBTTM Feature - No dead cycles between write and read  
◆
cycles  
◆
A Clock Enable (CEN) pin allows operation of the IDT71V65703/5903  
tobesuspendedaslongasnecessary.Allsynchronousinputsareignoredwhen  
CENishighandtheinternaldeviceregisterswillholdtheirpreviousvalues.  
There are three chip enable pins (CE1, CE2, CE2) that allow the  
usertodeselectthedevicewhendesired.Ifanyoneofthesethreeisnot  
assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.  
However,anypendingdatatransfers(readsorwrites)willbecompleted.  
Thedatabuswilltri-stateonecycleafterthechipisdeselectedorawrite  
isinitiated.  
TheIDT71V65703/5903haveanon-chipburstcounter.Intheburst  
mode,theIDT71V65703/5903canprovidefourcyclesofdataforasingle  
address presented to the SRAM. The order of the burst sequence is  
defined by the LBO input pin. The LBO pin selects between linear and  
interleaved burst sequence. The ADV/LD signal is used to load a new  
externaladdress(ADV/LD=LOW)orincrementtheinternalburstcounter  
(ADV/LD = HIGH).  
Internally synchronized output buffer enable eliminates the  
need to control OE  
Single R/W (READ/WRITE) control pin  
4-word burst capability (Interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
3.3V power supply (±5%)  
3.3V (±5%) I/O Supply (VDDQ)  
Power down controlled by ZZ input  
◆
◆
◆
◆
◆
◆
◆
◆
Packaged in a JEDEC standard 100-pin plastic thin quad  
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch  
ball grid array (fBGA).  
Description  
The IDT71V65703/5903 are 3.3V high-speed 9,437,184-bit  
(9 Megabit) synchronous SRAMs organized as 256K x 36 / 512K x 18.  
They are designed to eliminate dead bus cycles when turning the bus  
aroundbetweenreads andwrites,orwrites andreads.Thus theyhave  
been given the name ZBTTM, or Zero Bus Turnaround.  
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock  
TheIDT71V65703/5903SRAMsutilizeIDT’slatesthigh-performance  
CMOSprocessandarepackagedinaJEDECStandard14mmx20mm100-  
pinplasticthinquadflatpack(TQFP), 119 ballgridarray(BGA)and a 165  
fine pitchballgridarray(fBGA).  
PinDescriptionSummary  
A0-A18  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enables  
CE1, CE2, CE2  
Output Enable  
OE  
R/W  
Read/Write Signal  
Clock Enable  
CEN  
Individual Byte Write Selects  
Clock  
BW1, BW2, BW3, BW4  
CLK  
ADV/LD  
Advance Burst Address/Load New Address  
Linear/Interleaved Burst Order  
Sleep Mode  
Synchronous  
Static  
LBO  
ZZ  
Asynchronous  
Synchronous  
Static  
I/ O0-I/O31, I/OP1-I/OP4  
VDD, VDDQ  
Data Input/Output  
Core Power, I/O Power  
Ground  
Supply  
Supply  
VSS  
Static  
5298 tbl 01  
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.  
DECEMBER 2002  
1
©2002IntegratedDeviceTechnology,Inc.  
DSC-5298/03  
1234567...26

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IDT71V65903S85PFGI8 IDT

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IDT71V65903S85PFI IDT

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 		256K x 36, 512K x 18 3.3V Synchronous ZBT SRAMs
IDT71V65903S85PFI8 IDT

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 		ZBT SRAM, 512KX18, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, MO-136DJ, PLASTIC, TQ
IDT71V659S80BG IDT

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 		ZBT SRAM, 512KX18, 8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V67602 IDT

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 		256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Sin
IDT71V67602133BG IDT

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 		256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Sin
IDT71V67602133BGI IDT

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 		256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Sin
IDT71V67602133BQ IDT

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 		256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Sin
IDT71V67602133BQI IDT

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 		256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Sin
IDT71V67602133PF IDT

获取价格

 		256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Sin

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