Datasheet > IDT71V657S85PF

IDT71V657S85PF

更新时间： 2024-09-20 10:48:11

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
23页	322K
描述
ZBT SRAM, 256KX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100

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数据手册

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IDT71V657S85PF 数据手册

256K x 36, 512K x 18

Preliminary

IDT71V657

IDT71V659

3.3V Synchronous ZBT™ SRAMs

3.3V or 2.5V I/O, Burst Counter

Flow-Through Outputs

Features

◆

The IDT71V657/59 contain address, data-in and control signal

registers.Theoutputsareflow-through(nooutputdataregister).Output

enable is the only asynchronous signal and can be used to disable the

outputsatanygiventime.

256K x 36, 512K x 18 memory configurations

◆

Supports high performance system speed - 100 MHz

(7.5 ns Clock-to-Data Access)

ZBT^TMFeature - No dead cycles between write and read

◆

A Clock Enable (CEN) pin allows operation of the IDT71V657/59

to be suspended as long as necessary. All synchronous inputs are

ignoredwhen(CEN)ishighandtheinternaldeviceregisterswillholdtheir

previous values.

There are three chip enable pins (CE1, CE2, CE2) that allow the

user to deselect the device when desired. If any one of these three are

not asserted when ADV/LD is low, no new memory operation can be

initiated. However, any pending data transfers (reads or writes) will be

completed.Thedatabuswilltri-stateonecycleafterchipisdeselectedor

awriteisinitiated.

cycles

◆

Internally synchronized output buffer enable eliminates the

need to control OE

Single R/W (READ/WRITE) control pin

4-word burst capability (Interleaved or linear)

Individual byte write (BW1 - BW4) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply (±5%)

User selectable 3.3V (±5%) or 2.5V (±5%) I/O Supply (VDDQ)

◆

Packaged in a JEDEC standard 100-lead plastic thin

The IDT71V657/59 have an on-chip burst counter. In the burst

mode, the IDT71V657/59 can provide four cycles of data for a single

address presented to the SRAM. The order of the burst sequence is

defined by the LBO input pin. The LBO pin selects between linear and

interleaved burst sequence. The ADV/LD signal is used to load a new

externaladdress(ADV/LD=LOW)orincrementtheinternalburstcounter

(ADV/LD = HIGH).

The IDT71V657/59 SRAMs utilize IDTs latest high-performance

CMOSprocess,andarepackagedinaJEDECStandard14mmx20mm

100-lead plastic thin quad flatpack (TQFP) as well as a 119-lead ball

grid array (BGA).

quad flatpack (TQFP) and 119-lead ball grid array (BGA).

Description

The IDT71V657/59 are 3.3V high-speed 9,437,184-bit

(9 Megabit) synchronous SRAMs organized as 256K x 36 / 512K x

18. They are designed to eliminate dead bus cycles when turning the

bus around between reads and writes, or writes and reads. Thus

they have been given the name ZBT^TM, or Zero Bus Turnaround.

AddressandcontrolsignalsareappliedtotheSRAMduringoneclock

cycle,andonthenextclockcycletheassociateddatacycleoccurs,be

it read or write.

PinDescriptionSummary

A -A

Address Inputs

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enables

CE , CE , CE

Output Enable

R/W

Read/Write Signal

Clock Enable

CEN

Individual Byte Write Selects

Clock

BW , BW , BW , BW

CLK

ADV/LD

Advance burst address / Load new address

Linear / Interleaved Burst Order

Data Input / Output

Core Power, I/O Power

Ground

Synchronous

Static

LBO

I/O -I/O , I/O -I/O

Synchronous

Static

DD DDQ

, V

Supply

Static

5001 tbl 01

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.

AUGUST1999

DSC-5001/02

12 3 4 5 6 7...23

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与IDT71V657S85PF相关器件

型号	品牌	获取价格	描述	数据表
IDT71V65802	IDT	获取价格	256K x 36, 512K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V65802100BQI	IDT	获取价格	ZBT SRAM, 512KX18, 5ns, CMOS, PBGA165, 13 X 15 MM, FPBGA-165
IDT71V65802100PFI	IDT	获取价格	ZBT SRAM, 512KX18, 5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, 1 MM PITCH, PLASTIC, MO
IDT71V65802133BQ	IDT	获取价格	ZBT SRAM, 512KX18, 4.2ns, CMOS, PBGA165, 13 X 15 MM, FPBGA-165
IDT71V65802133PF	IDT	获取价格	ZBT SRAM, 512KX18, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, 1 MM PITCH, PLASTIC,
IDT71V65802133PFI	IDT	获取价格	ZBT SRAM, 512KX18, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, 1 MM PITCH, PLASTIC,
IDT71V65802150BGI	IDT	获取价格	ZBT SRAM, 512KX18, 3.8ns, CMOS, PBGA119, 14 X 22 MM, MS-028AA, BGA-119
IDT71V65802150BQ	IDT	获取价格	ZBT SRAM, 512KX18, 3.8ns, CMOS, PBGA165, 13 X 15 MM, FPBGA-165
IDT71V65802150BQI	IDT	获取价格	ZBT SRAM, 512KX18, 3.8ns, CMOS, PBGA165, 13 X 15 MM, FPBGA-165
IDT71V65802150PF	IDT	获取价格	ZBT SRAM, 512KX18, 3.8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, 1 MM PITCH, PLASTIC,

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