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IDT71V65603S150BGG8 PDF预览

IDT71V65603S150BGG8

更新时间： 2024-09-18 20:55:07
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
26页 485K
描述
ZBT SRAM, 256KX36, 3.8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MO-028AA, BGA-119

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IDT71V65603S150BGG8 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：BGA
包装说明：BGA,针数：119
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.1
Is Samacsys：N最长访问时间：3.8 ns
其他特性：PIPELINED ARCHITECTUREJESD-30 代码：R-PBGA-B119
JESD-609代码：e1长度：22 mm
内存密度：9437184 bit内存集成电路类型：ZBT SRAM
内存宽度：36湿度敏感等级：3
功能数量：1端子数量：119
字数：262144 words字数代码：256000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：256KX36
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装形状：RECTANGULAR封装形式：GRID ARRAY
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：2.36 mm
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：TIN SILVER COPPER端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：30宽度：14 mm
Base Number Matches：1

IDT71V65603S150BGG8 数据手册

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256K x 36, 512K x 18  
3.3V Synchronous ZBT™ SRAMs  
ZBT™Feature  
IDT71V65603/Z  
IDT71V65803/Z  
3.3V I/O, Burst Counter  
PipelinedOutputs  
Features  
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock  
cycle,andtwocycleslatertheassociateddatacycleoccurs,beitreadorwrite.  
TheIDT71V65603/5803containdataI/O,addressandcontrolsignal  
registers.Outputenableistheonlyasynchronoussignalandcanbeused  
todisabletheoutputsatanygiventime.  
◆
256K x 36, 512K x 18 memory configurations  
◆
Supports high performance system speed - 150MHz  
(3.8ns Clock-to-Data Access)  
ZBTTM Feature - No dead cycles between write and read cycles  
◆
◆
Internally synchronized output buffer enable eliminates the  
AClockEnable(CEN)pinallowsoperationoftheIDT71V65603/5803to  
besuspendedaslongasnecessary.Allsynchronousinputsareignoredwhen  
(CEN)ishighandtheinternaldeviceregisterswillholdtheirpreviousvalues.  
Therearethreechipenablepins(CE1, CE2, CE2)thatallowtheuser  
todeselectthedevicewhendesired.Ifanyoneofthesethreearenotasserted  
whenADV/LDislow,nonewmemoryoperationcanbeinitiated.However,  
anypendingdatatransfers(readsorwrites)willbecompleted.Thedatabus  
willtri-statetwocyclesafterchipisdeselectedorawriteisinitiated.  
TheIDT71V65603/5803haveanon-chipburstcounter.Intheburst  
mode,theIDT71V65603/5803canprovidefourcyclesofdataforasingle  
address presented to the SRAM. The order of the burst sequence is  
defined by the LBO input pin. The LBO pin selects between linear and  
interleaved burst sequence. The ADV/LDsignal is used to load a new  
externaladdress(ADV/LD=LOW) orincrementtheinternalburstcounter  
(ADV/LD = HIGH).  
need to control OE  
Single R/W (READ/WRITE) control pin  
Positive clock-edge triggered address, data, and control  
signal registers for fully pipelined applications  
4-word burst capability (interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
3.3V power supply (±5%)  
3.3V I/O Supply (VDDQ)  
Power down controlled by ZZ input  
Packaged in a JEDEC standard 100-pin plastic thin quad  
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch  
ball grid array(fBGA).  
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◆
◆
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◆
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Description  
The IDT71V65603/5803 are 3.3V high-speed 9,437,184-bit  
(9Megabit)synchronousSRAMS.Theyaredesignedtoeliminatedeadbus  
cycleswhenturningthebusaroundbetweenreadsandwrites, orwritesand  
reads.Thus,theyhavebeengiventhenameZBTTM,orZeroBusTurnaround.  
The IDT71V65603/5803 SRAM utilize IDT's latest high-performance  
CMOSprocess,andarepackagedinaJEDECStandard14mmx20mm100-  
pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray(BGA)and  
165 fine pitch ball grid array (fBGA) .  
PinDescriptionSummary  
A
0-A18  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enables  
CE1  
, CE  
2
, CE  
2
Output Enable  
OE  
R/W  
Read/Write Signal  
Clock Enable  
CEN  
Individual Byte Write Selects  
Clock  
BW  
1
, BW  
2
, BW  
3
, BW  
4
CLK  
ADV/LD  
LBO  
Advance burst address / Load new address  
Linear / Interleaved Burst Order  
Sleep Mode  
Synchronous  
Static  
ZZ  
Asynchronous  
Synchronous  
Static  
I/O  
0
-I/O31, I/OP1-I/OP4  
Data Input / Output  
Core Power, I/O Power  
Ground  
V
V
DD, VDDQ  
SS  
Supply  
Supply  
Static  
5304 tbl 01  
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.  
OCTOBER 2008  
1
©2007IntegratedDeviceTechnology,Inc.  
DSC-5304/07  
1234567...26

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与IDT71V65603S150BGG8相关器件

型号 品牌 获取价格 描述 数据表
IDT71V65603S150BGGI IDT

获取价格

 		ZBT SRAM, 256KX36, 3.8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MO-028AA, BGA-119
IDT71V65603S150BGI IDT

获取价格

 		256K x 36, 512K x 18 3.3V Synchronous ZBT SRAMs
IDT71V65603S150BQ IDT

获取价格

 		256K x 36, 512K x 18 3.3V Synchronous ZBT SRAMs
IDT71V65603S150BQ8 IDT

获取价格

 		ZBT SRAM, 256KX36, 3.8ns, CMOS, PBGA165, 13 X 15 MM, BGA-165
IDT71V65603S150BQG IDT

获取价格

 		ZBT SRAM, 256KX36, 3.8ns, CMOS, PBGA165, FBGA-165
IDT71V65603S150BQGI IDT

获取价格

 		ZBT SRAM, 256KX36, 3.8ns, CMOS, PBGA165, 13 X 15 MM, BGA-165
IDT71V65603S150BQI IDT

获取价格

 		256K x 36, 512K x 18 3.3V Synchronous ZBT SRAMs
IDT71V65603S150BQI8 IDT

获取价格

 		ZBT SRAM, 256KX36, 3.8ns, CMOS, PBGA165, 13 X 15 MM, BGA-165
IDT71V65603S150PF IDT

获取价格

 		256K x 36, 512K x 18 3.3V Synchronous ZBT SRAMs
IDT71V65603S150PFG IDT

获取价格

 		ZBT SRAM, 256KX36, 3.8ns, CMOS, PQFP100, PLASTIC, MO-136, TQFP-100

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