Datasheet > IDT71V65602S-150PF

IDT71V65602S-150PF

更新时间： 2024-11-06 23:05:07

品牌	Logo	应用领域
艾迪悌 - IDT		计数器静态存储器
页数	文件大小	规格书
26页	971K
描述
256K x 36, 512K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

IDT71V65602S-150PF 数据手册

浏览型号IDT71V65602S-150PF的Datasheet PDF文件第2页

浏览型号IDT71V65602S-150PF的Datasheet PDF文件第3页

浏览型号IDT71V65602S-150PF的Datasheet PDF文件第4页

浏览型号IDT71V65602S-150PF的Datasheet PDF文件第5页

浏览型号IDT71V65602S-150PF的Datasheet PDF文件第6页

浏览型号IDT71V65602S-150PF的Datasheet PDF文件第7页

256K x 36, 512K x 18

IDT71V65602

IDT71V65802

3.3VSynchronousZBT™SRAMs

2.5V I/O, Burst Counter

PipelinedOutputs

Features

AddressandcontrolsignalsareappliedtotheSRAMduringoneclock

cycle,andtwocycleslatertheassociateddatacycleoccurs,beitreadorwrite.

The IDT71V65602/5802 contain data I/O, address and control signal

registers.Outputenableistheonlyasynchronoussignalandcanbeusedto

disabletheoutputsatanygiventime.

A Clock Enable (CEN) pin allows operation of the IDT71V65602/5802

tobesuspendedaslongasnecessary.Allsynchronousinputsareignored

when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious

values.

There are three chip enable pins (CE¹, CE2, CE2) that allow the

usertodeselectthedevicewhendesired. Ifanyoneofthesethreearenot

assertedwhenADV/LDislow, nonewmemoryoperationcanbeinitiated.

However,anypendingdatatransfers(readsorwrites)willbecompleted.The

databuswilltri-statetwocyclesafterchipisdeselectedorawriteisinitiated.

The IDT71V65602/5802 have an on-chip burst counter. In the burst

mode, the IDT71V65602/5802 can provide four cycles of data for a single

addresspresentedtotheSRAM.Theorderoftheburstsequenceisdefined

bytheLBOinputpin.TheLBOpinselectsbetweenlinearandinterleavedburst

sequence.TheADV/LDsignalisusedtoloadanewexternaladdress(ADV/

LD=LOW) orincrementtheinternalburstcounter(ADV/LD=HIGH).

The IDT71V65602/5802 SRAM utilize IDT's latest high-performance

◆

256K x 36, 512K x 18 memory configurations

◆

Supports high performance system speed - 150MHz

(3.8ns Clock-to-Data Access)

ZBT Feature - No dead cycles between write and read cycles

Internally synchronized output buffer enable eliminates the

◆

need to control OE

Single R/W (READ/WRITE) control pin

◆

Positive clock-edge triggered address, data, and control

signal registers for fully pipelined applications

4-word burst capability (interleaved or linear)

Individual byte write (BW¹- BW⁴) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply (±5%)

2.5V I/O Supply (VDDQ)

Power down controlled by ZZ input

Packaged in a JEDEC standard 100-pin plastic thin quad and

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array (fBGA)

◆

Description

The IDT71V65602/5802 are 3.3V high-speed 9,437,184-bit CMOSprocess,andarepackagedinaJEDECStandard14mmx20mm100-

(9Megabit)synchronousSRAMs.Theyaredesignedtoeliminatedead pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray(BGA)

bus cycles when turning the bus around between reads and writes, or and a 165 fine pitch ball grid array (fBGA).

writes andreads.Thus,theyhavebeengiventhenameZBT ,orZero

Bus Turnaround.

PinDescriptionSummary

A0-A18

Address Inputs

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enables

CE1, CE2, CE2

Output Enable

R/W

Read/Write Signal

Clock Enable

CEN

Individual Byte Write Selects

Clock

BW1, BW2, BW3, BW4

CLK

ADV/LD

Advance burstaddress / Load new address

Linear / Interleaved Burst Order

Sleep Mode

Synchronous

Static

LBO

Asynchronous

Synchronous

Static

I/O0-I/O31, I/OP1-I/OP4

VDD, VDDQ

Data Input / Output

Core Power, I/O Power

Ground

Supply

VSS

Static

5303 tbl 01

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.

OCTOBER 2004

DSC-5303/05

12 3 4 5 6 7...26

中文翻译

下载PDF

与IDT71V65602S-150PF相关器件

型号	品牌	获取价格	描述	数据表
IDT71V65602S150PFG8	IDT	获取价格	ZBT SRAM, 256KX36, 3.8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, GREEN, PLASTIC, TQFP-
IDT71V65602S150PFI	IDT	获取价格	256K x 36, 512K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V65602S-150PFI	IDT	获取价格	256K x 36, 512K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V65602S166BG	IDT	获取价格	ZBT SRAM, 256KX36, 3.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V65602S166PF	IDT	获取价格	ZBT SRAM, 256KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100
IDT71V65602Z100BGI	IDT	获取价格	ZBT SRAM, 256KX36, 5ns, CMOS, PBGA119, 14 X 22 MM, MS-028AA, BGA-119
IDT71V65602Z100BQ	IDT	获取价格	ZBT SRAM, 256KX36, 5ns, CMOS, PBGA165, 13 X 15 MM, FPBGA-165
IDT71V65602Z133BGI	IDT	获取价格	ZBT SRAM, 256KX36, 4.2ns, CMOS, PBGA119, 14 X 22 MM, MS-028AA, BGA-119
IDT71V65602Z133BQ	IDT	获取价格	ZBT SRAM, 256KX36, 4.2ns, CMOS, PBGA165, 13 X 15 MM, FPBGA-165
IDT71V65602Z133PFI	IDT	获取价格	ZBT SRAM, 256KX36, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, 1 MM PITCH, PLASTIC,

与IDT71V65602S-150PF相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

19
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

16
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

39
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

37

产品中心

服务支持

精选活动

关于我们

帮助中心

IDT71V65602S-150PF

IDT71V65602S-150PF 数据手册

与IDT71V65602S-150PF相关器件

与IDT71V65602S-150PF相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

IDT71V65602S-150PF

IDT71V65602S-150PF 数据手册

与IDT71V65602S-150PF相关器件

与IDT71V65602S-150PF相关文章

您还可以找

您在本页遇到什么问题？