256K x 36, 512K x 18
IDT71V65602
IDT71V65802
3.3VSynchronousZBT™SRAMs
2.5V I/O, Burst Counter
PipelinedOutputs
Features
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock
cycle,andtwocycleslatertheassociateddatacycleoccurs,beitreadorwrite.
The IDT71V65602/5802 contain data I/O, address and control signal
registers.Outputenableistheonlyasynchronoussignalandcanbeusedto
disabletheoutputsatanygiventime.
A Clock Enable (CEN) pin allows operation of the IDT71V65602/5802
tobesuspendedaslongasnecessary.Allsynchronousinputsareignored
when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious
values.
There are three chip enable pins (CE1, CE2, CE2) that allow the
usertodeselectthedevicewhendesired. Ifanyoneofthesethreearenot
assertedwhenADV/LDislow, nonewmemoryoperationcanbeinitiated.
However,anypendingdatatransfers(readsorwrites)willbecompleted.The
databuswilltri-statetwocyclesafterchipisdeselectedorawriteisinitiated.
The IDT71V65602/5802 have an on-chip burst counter. In the burst
mode, the IDT71V65602/5802 can provide four cycles of data for a single
addresspresentedtotheSRAM.Theorderoftheburstsequenceisdefined
bytheLBOinputpin.TheLBOpinselectsbetweenlinearandinterleavedburst
sequence.TheADV/LDsignalisusedtoloadanewexternaladdress(ADV/
LD=LOW) orincrementtheinternalburstcounter(ADV/LD=HIGH).
The IDT71V65602/5802 SRAM utilize IDT's latest high-performance
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256K x 36, 512K x 18 memory configurations
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Supports high performance system speed - 150MHz
(3.8ns Clock-to-Data Access)
ZBT Feature - No dead cycles between write and read cycles
Internally synchronized output buffer enable eliminates the
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TM
need to control OE
Single R/W (READ/WRITE) control pin
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Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW1 - BW4) control (May tie active)
Three chip enables for simple depth expansion
3.3V power supply (±5%)
2.5V I/O Supply (VDDQ)
Power down controlled by ZZ input
Packaged in a JEDEC standard 100-pin plastic thin quad and
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA)
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Description
The IDT71V65602/5802 are 3.3V high-speed 9,437,184-bit CMOSprocess,andarepackagedinaJEDECStandard14mmx20mm100-
(9Megabit)synchronousSRAMs.Theyaredesignedtoeliminatedead pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray(BGA)
bus cycles when turning the bus around between reads and writes, or and a 165 fine pitch ball grid array (fBGA).
TM
writes andreads.Thus,theyhavebeengiventhenameZBT ,orZero
Bus Turnaround.
PinDescriptionSummary
A0-A18
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Chip Enables
CE1, CE2, CE2
Output Enable
OE
R/W
Read/Write Signal
Clock Enable
CEN
Individual Byte Write Selects
Clock
BW1, BW2, BW3, BW4
CLK
ADV/LD
Advance burstaddress / Load new address
Linear / Interleaved Burst Order
Sleep Mode
Synchronous
Static
LBO
ZZ
Asynchronous
Synchronous
Static
I/O0-I/O31, I/OP1-I/OP4
VDD, VDDQ
Data Input / Output
Core Power, I/O Power
Ground
Supply
Supply
VSS
Static
5303 tbl 01
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.
OCTOBER 2004
1
©2004IntegratedDeviceTechnology,Inc.
DSC-5303/05