Datasheet > IDT71V65602S-133PFI

IDT71V65602S-133PFI

更新时间： 2024-11-26 22:06:19

品牌	Logo	应用领域
艾迪悌 - IDT		计数器静态存储器
页数	文件大小	规格书
26页	971K
描述
256K x 36, 512K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs

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256K x 36, 512K x 18

IDT71V65602

IDT71V65802

3.3VSynchronousZBT™SRAMs

2.5V I/O, Burst Counter

PipelinedOutputs

Features

AddressandcontrolsignalsareappliedtotheSRAMduringoneclock

cycle,andtwocycleslatertheassociateddatacycleoccurs,beitreadorwrite.

The IDT71V65602/5802 contain data I/O, address and control signal

registers.Outputenableistheonlyasynchronoussignalandcanbeusedto

disabletheoutputsatanygiventime.

A Clock Enable (CEN) pin allows operation of the IDT71V65602/5802

tobesuspendedaslongasnecessary.Allsynchronousinputsareignored

when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious

values.

There are three chip enable pins (CE¹, CE2, CE2) that allow the

usertodeselectthedevicewhendesired. Ifanyoneofthesethreearenot

assertedwhenADV/LDislow, nonewmemoryoperationcanbeinitiated.

However,anypendingdatatransfers(readsorwrites)willbecompleted.The

databuswilltri-statetwocyclesafterchipisdeselectedorawriteisinitiated.

The IDT71V65602/5802 have an on-chip burst counter. In the burst

mode, the IDT71V65602/5802 can provide four cycles of data for a single

addresspresentedtotheSRAM.Theorderoftheburstsequenceisdefined

bytheLBOinputpin.TheLBOpinselectsbetweenlinearandinterleavedburst

sequence.TheADV/LDsignalisusedtoloadanewexternaladdress(ADV/

LD=LOW) orincrementtheinternalburstcounter(ADV/LD=HIGH).

The IDT71V65602/5802 SRAM utilize IDT's latest high-performance

◆

256K x 36, 512K x 18 memory configurations

◆

Supports high performance system speed - 150MHz

(3.8ns Clock-to-Data Access)

ZBT Feature - No dead cycles between write and read cycles

Internally synchronized output buffer enable eliminates the

◆

need to control OE

Single R/W (READ/WRITE) control pin

◆

Positive clock-edge triggered address, data, and control

signal registers for fully pipelined applications

4-word burst capability (interleaved or linear)

Individual byte write (BW¹- BW⁴) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply (±5%)

2.5V I/O Supply (VDDQ)

Power down controlled by ZZ input

Packaged in a JEDEC standard 100-pin plastic thin quad and

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array (fBGA)

◆

Description

The IDT71V65602/5802 are 3.3V high-speed 9,437,184-bit CMOSprocess,andarepackagedinaJEDECStandard14mmx20mm100-

(9Megabit)synchronousSRAMs.Theyaredesignedtoeliminatedead pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray(BGA)

bus cycles when turning the bus around between reads and writes, or and a 165 fine pitch ball grid array (fBGA).

writes andreads.Thus,theyhavebeengiventhenameZBT ,orZero

Bus Turnaround.

PinDescriptionSummary

A0-A18

Address Inputs

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enables

CE1, CE2, CE2

Output Enable

R/W

Read/Write Signal

Clock Enable

CEN

Individual Byte Write Selects

Clock

BW1, BW2, BW3, BW4

CLK

ADV/LD

Advance burstaddress / Load new address

Linear / Interleaved Burst Order

Sleep Mode

Synchronous

Static

LBO

Asynchronous

Synchronous

Static

I/O0-I/O31, I/OP1-I/OP4

VDD, VDDQ

Data Input / Output

Core Power, I/O Power

Ground

Supply

VSS

Static

5303 tbl 01

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.

OCTOBER 2004

DSC-5303/05

12 3 4 5 6 7...26

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与IDT71V65602S-133PFI相关器件

型号	品牌	获取价格	描述	数据表
IDT71V65602S133PFI8	IDT	获取价格	ZBT SRAM, 256KX36, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
IDT71V65602S150B	IDT	获取价格	ZBT SRAM, 256KX36, 3.8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V65602S150BG	IDT	获取价格	256K x 36, 512K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V65602S-150BG	IDT	获取价格	256K x 36, 512K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V65602S150BGG	IDT	获取价格	ZBT SRAM, 256KX36, 3.8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V65602S150BGI	IDT	获取价格	256K x 36, 512K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V65602S-150BGI	IDT	获取价格	256K x 36, 512K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V65602S150BQ	IDT	获取价格	256K x 36, 512K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V65602S-150BQ	IDT	获取价格	256K x 36, 512K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V65602S150BQI	IDT	获取价格	256K x 36, 512K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs

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