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IDT71V547S75PFG8

更新时间： 2024-09-18 14:51:27
品牌 Logo 应用领域
艾迪悌 - IDT 时钟静态存储器内存集成电路
页数 文件大小 规格书
19页 160K
描述
ZBT SRAM, 128KX36, 7.5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100

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IDT71V547S75PFG8 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：QFP
包装说明：14 X 20 MM, PLASTIC, TQFP-100针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.47
Is Samacsys：N最长访问时间：7.5 ns
其他特性：BURST COUNTER最大时钟频率 (fCLK)：100 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
JESD-609代码：e3长度：20 mm
内存密度：4718592 bit内存集成电路类型：ZBT SRAM
内存宽度：36湿度敏感等级：3
功能数量：1端子数量：100
字数：131072 words字数代码：128000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：128KX36
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
座面最大高度：1.6 mm最大待机电流：0.04 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.275 mA最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Matte Tin (Sn) - annealed
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：14 mmBase Number Matches：1

IDT71V547S75PFG8 数据手册

 浏览型号IDT71V547S75PFG8的Datasheet PDF文件第2页浏览型号IDT71V547S75PFG8的Datasheet PDF文件第3页浏览型号IDT71V547S75PFG8的Datasheet PDF文件第4页浏览型号IDT71V547S75PFG8的Datasheet PDF文件第5页浏览型号IDT71V547S75PFG8的Datasheet PDF文件第6页浏览型号IDT71V547S75PFG8的Datasheet PDF文件第7页 
128K X 36, 3.3V Synchronous  
IDT71V547  
SRAM with ZBT™ Feature, Burst  
Counter and Flow-Through Outputs  
Features  
◆
128K x 36 memory configuration, flow-through outputs  
TheIDT71V547containsaddress,data-inandcontrolsignalregisters.  
Theoutputsareflow-through(nooutputdataregister).Outputenableis  
theonlyasynchronoussignalandcanbeusedtodisabletheoutputsat  
anygiventime.  
◆
Supports high performance system speed - 95 MHz  
(8ns Clock-to-Data Access)  
ZBTTM Feature - No dead cycles between write and read  
◆
cycles  
A Clock Enable (CEN) pin allows operation of the IDT71V547 to  
be suspended as long as necessary. All synchronous inputs are  
ignored when CENis high and the internal device registers will hold  
their previous values.  
Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser  
todeselectthedevicewhendesired. Ifanyoneofthesethreeisnotactive  
whenADV/LDislow,nonewmemoryoperationcanbeinitiatedandany  
burstinprogressisstopped.However,anypendingdatatransfers(reads  
orwrites)willbecompleted.Thedatabuswilltri-stateonecycleafterthe  
chipwasdeselectedorwriteinitiated.  
◆
Internally synchronized signal eliminates the need to  
control OE  
Single R/W (READ/WRITE) control pin  
4-word burst capability (Interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
Single 3.3V power supply (±5%)  
Packaged in a JEDEC standard 100-pin TQFP package  
◆
◆
◆
◆
◆
◆
TheIDT71V547hasanon-chipburstcounter. Intheburstmode,the  
IDT71V547canprovidefourcyclesofdataforasingleaddresspresented  
totheSRAM.TheorderoftheburstsequenceisdefinedbytheLBOinput  
pin. TheLBOpinselectsbetweenlinearandinterleavedburstsequence.  
The ADV/LDsignalis usedtoloada newexternaladdress (ADV/LD=  
LOW)orincrementtheinternalburstcounter(ADV/LD=HIGH).  
TheIDT71V547SRAMutilizesIDT'shigh-performance,high-volume  
3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x  
20mm100-pinthinplasticquadflatpack(TQFP)forhighboarddensity.  
Description  
The IDT71V547 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)  
synchronousSRAMorganizedas128Kx36bits. Itisdesignedtoeliminate  
deadbuscycleswhenturningthebusaroundbetweenreadsandwrites,  
orwritesandreads.ThusithasbeengiventhenameZBTTM,orZeroBus  
Turn-around.  
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock  
cycle,andonthenextclockcycle,itsassociateddatacycleoccurs,beit  
read or write.  
PinDescriptionSummary  
0
16  
A - A  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Three Chip Enables  
Output Enable  
1
2
2
CE , CE , CE  
OE  
R/W  
Read/Write Signal  
Clock Enable  
CEN  
Individual Byte Write Selects  
Clock  
1
2
3
4
BW , BW , BW , BW  
CLK  
ADV/LD  
Advance Burst Address / Load New Address  
Linear / Interleaved Burst Order  
Data Input/Output  
3.3V Power  
Synchronous  
Static  
LBO  
0
31  
P1  
I/O - I/O , I/O -  
Synchronous  
Static  
P4  
I/O  
DD  
V
Supply  
Supply  
SS  
V
Ground  
Static  
3822 tbl 01  
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.  
DECEMBER 1999  
1
DSC-3822/03  
©1999IntegratedDeviceTechnology,Inc.  
1234567...19

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IDT71V547S80PF IDT

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 		128K X 36, 3.3V Synchronous SRAM with ZBT Feature, Burst Counter and Flow-Through Outputs
IDT71V547S80PFG IDT

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 		ZBT SRAM, 128KX36, 8ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100
IDT71V547S80PFI IDT

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 		128K X 36, 3.3V Synchronous SRAM with ZBT Feature, Burst Counter and Flow-Through Outputs
IDT71V547S85PF IDT

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 		128K X 36, 3.3V Synchronous SRAM with ZBT Feature, Burst Counter and Flow-Through Outputs
IDT71V547S85PF8 IDT

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 		ZBT SRAM, 128KX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100
IDT71V547S85PF9 IDT

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 		ZBT SRAM, 128KX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100
IDT71V547S85PFG IDT

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 		ZBT SRAM, 128KX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100
IDT71V547S85PFGI8 IDT

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 		ZBT SRAM, 128KX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100
IDT71V547S85PFI IDT

获取价格

 		128K X 36, 3.3V Synchronous SRAM with ZBT Feature, Burst Counter and Flow-Through Outputs
IDT71V547S85PFI8 IDT

获取价格

 		ZBT SRAM, 128KX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100

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