128K x 36, 256K x 18
Preliminary
IDT71V3566
IDT71V3568
SmartZBT™3.3VSynchronousSRAMs
3.3V I/O, Burst Counter
PipelinedOutputs
Features
Description
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128K x 36, 256K x 18 memory configurations
TheIDT71V3566/68are3.3Vhigh-speed4,718,592-bit(4.5Mega-
bit) synchronous SRAMs. They are designed to eliminate dead bus
cycles when turning the bus around between reads and writes, or
writes and reads. Thus, they have been given the name ZBTTM, or
Zero Bus Turnaround.
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Supports high performance system speed - from 66MHz to
133MHz
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ZBTTM Feature - No dead cycles between write and read
cycles
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Smart ZBTTM Feature - Eases system timing requirements
Address and control signals are applied to the SRAM during one
clockcycle,andtwocycleslatertheassociateddatacycleoccurs,beit
read or write.
and reduces the likelihood of bus contention
With Smart ZBTTM the output turn-on (tCLZ) is adaptable to
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the user's system and is a function of the cycle time
Backward compatible with IDT's existing ZBT offerings
Internally synchronized output buffer enable eliminates the and reads. Traditionally, SRAMs are designed with fast turn-on times
TheIDT71V3566/68offertheuseraSmartfunctionalitywhichsimplifies
systemtimingrequirementswhenturningthebusaroundbetweenwrites
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need to control OE
(tCLZ)inordertomeettherequirementsofhighspeedapplications.This
fastturn-onmayleadtobuscontentionatslowerspeeds,i.e.133MHzand
slower,sincethesedesignsoftenuselessaggressiveASICs/controllers
withlooseturn-offparameters(tCHZ).Thusatslowerspeeds,moremargin
ontheRAM'stCLZmaybeneededtocompensatefortheslowturn-offof
theASIC/controller.TheIDT71V3566/68havetheabilitytoprovidethis
extra marginbyallowingtCLZ toadapttothe user's system.
WiththeSmartZBTTM feature,theoutputturn-ontime(tCLZ)adaptsto
theuser'ssystemandissolelyafunctionofcycletime(tCYC).Thuswith
SmartZBTTM,tCLZisindependentofprocess,voltage,andtemperature
variations.Withthisdeterministicoutputturn-onfeature,theguessworkof
when the SRAM begins to drive the bus is removed, therefore easing
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Single R/W (READ/WRITE) control pin
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW1 - BW4) control (May tie active)
Three chip enables for simple depth expansion
3.3V power supply (±5%)
3.3V I/O Supply (VDDQ)
Packaged in a JEDEC standard 100-lead plastic thin quad
flatpack (TQFP) and 119-lead ball grid array (BGA).
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PinDescriptionSummary
A
0
-A17
Addres s Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Synchronous
Synchronous
As ynchronous
Synchronous
Synchronous
Synchronous
N/A
Chip Enables
CE
1
, CE
2
,
CE
2
Output Enable
OE
R/
W
Re ad/Write Signal
Clock Enable
CEN
BW
Individual Byte Write Se le cts
Clock
1
,
BW
2
,
BW
3
,
BW
4
CLK
ADV/LD
Advance burst addre ss / Load new addre ss
Line ar / Inte rle aved Burs t Orde r
Data Input / Outp ut
Core Powe r, I/O Power
Ground
Synchronous
Static
LBO
I/O
0
-I/O31, I/OP 1-I/OP 4
DD, VDDQ
S S
Synchronous
Static
V
Supply
Supply
V
Static
5295 tbl 01
ZBT and ZeroBus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
Smart ZBT and Smart Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is also supported by Micron Technology, Inc.
DECEMBER 1999
1
©1999IntegratedDeviceTechnology,Inc.
DSC-5295/00