5秒后页面跳转
IDT71V2579S85BQI PDF预览

IDT71V2579S85BQI

更新时间: 2024-11-21 05:31:39
品牌 Logo 应用领域
艾迪悌 - IDT 计数器存储内存集成电路静态存储器时钟
页数 文件大小 规格书
22页 291K
描述
128K x 36,256K x 18 3.3V Synchronous SRAMs 2.5V I/O,Flow-Through Outputs Burst Counter,Single Cycle Deselect

IDT71V2579S85BQI 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:BGA包装说明:FBGA-165
针数:165Reach Compliance Code:not_compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.92Is Samacsys:N
最长访问时间:8.5 ns其他特性:FLOW-THROUGH ARCHITECTURE
最大时钟频率 (fCLK):87 MHzI/O 类型:COMMON
JESD-30 代码:R-PBGA-B165JESD-609代码:e0
长度:15 mm内存密度:4718592 bit
内存集成电路类型:CACHE SRAM内存宽度:18
湿度敏感等级:3功能数量:1
端子数量:165字数:262144 words
字数代码:256000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:256KX18输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TBGA
封装等效代码:BGA165,11X15,40封装形状:RECTANGULAR
封装形式:GRID ARRAY, THIN PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:2.5,3.3 V
认证状态:Not Qualified座面最大高度:1.2 mm
最大待机电流:0.035 A最小待机电流:3.14 V
子类别:SRAMs最大压摆率:0.19 mA
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn63Pb37)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:20宽度:13 mm
Base Number Matches:1

IDT71V2579S85BQI 数据手册

 浏览型号IDT71V2579S85BQI的Datasheet PDF文件第2页浏览型号IDT71V2579S85BQI的Datasheet PDF文件第3页浏览型号IDT71V2579S85BQI的Datasheet PDF文件第4页浏览型号IDT71V2579S85BQI的Datasheet PDF文件第5页浏览型号IDT71V2579S85BQI的Datasheet PDF文件第6页浏览型号IDT71V2579S85BQI的Datasheet PDF文件第7页 
IDT71V2577S  
IDT71V2579S  
IDT71V2577SA  
IDT71V2579SA  
128K x 36, 256K x 18  
3.3V Synchronous SRAMs  
2.5V I/O, Flow-Through Outputs  
Burst Counter, Single Cycle Deselect  
Description  
Features  
The IDT71V2577/79 are high-speed SRAMs organized as  
128Kx36/256Kx18.TheIDT71V2577/79SRAMs containwrite,data,  
address andcontrolregisters.Therearenoregisters inthedataoutput  
path (flow-through architecture). Internal logic allows the SRAM to  
generateaself-timedwritebaseduponadecisionwhichcanbeleftuntil  
128K x 36, 256K x 18 memory configurations  
Supports fast access times:  
Commercial:  
– 7.5ns up to 117MHz clock frequency  
CommercialandIndustrial:  
– 8.0ns up to 100MHz clock frequency  
– 8.5ns up to 87MHz clock frequency  
LBO input selects interleaved or linear burst mode  
Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite  
enable (BWE), and byte writes (BWx)  
3.3V core power supply  
Power down controlled by ZZ input  
2.5V I/O  
Optional - Boundary Scan JTAG Interface (IEEE 1149.1  
compliant)  
Packaged in a JEDEC Standard 100-pin plastic thin quad  
flatpack(TQFP),119ballgridarray(BGA)and165finepitchball  
grid array (fBGA)  
theendofthewritecycle.  
Theburstmodefeatureoffersthehighestlevelofperformancetothe  
systemdesigner,astheIDT71V2577/79canprovidefourcyclesofdata  
fora single address presentedtothe SRAM. Aninternalburstaddress  
counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe  
accesssequence.Thefirstcycleofoutputdatawillflow-throughfromthe  
arrayafteraclock-to-dataaccesstimedelayfromtherisingclockedgeof  
the same cycle. If burst mode operation is selected (ADV=LOW), the  
subsequentthreecyclesofoutputdatawillbeavailabletotheuseronthe  
next three rising clock edges. The order of these three addresses are  
definedbytheinternalburstcounterandtheLBOinputpin.  
The IDT71V2577/79 SRAMs utilize IDT’s latest high-performance  
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm  
100-pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray  
(BGA) and a 165 fine pitch ball grid array (fBGA).  
PinDescriptionSummary  
A0-A17  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Synchronous  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
Chip Enable  
CE  
CS0, CS1  
OE  
Chip Selects  
Output Enable  
Global Write Enable  
Byte Write Enable  
Individual Byte Write Selects  
GW  
BWE  
(1)  
BW1, BW2, BW3, BW4  
CLK  
ADV  
ADSC  
ADSP  
LBO  
Clock  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Output  
Input  
Input  
I/O  
N/A  
Synchronous  
Synchronous  
Synchronous  
DC  
Burst Address Advance  
Address Status (Cache Controller)  
Address Status (Processor)  
Linear / Interleaved Burst Order  
Test Mode Select  
Test Data Input  
TMS  
TDI  
Synchronous  
Synchronous  
N/A  
TCK  
TDO  
Test Clock  
Test Data Output  
Synchronous  
Asynchronous  
Asynchronous  
Synchronous  
N/A  
JTAG Reset (Optional)  
Sleep Mode  
TRST  
ZZ  
I/O0-I/O31, I/OP1-I/OP4  
VDD, VDDQ  
VSS  
Data Input / Output  
Core Power, I/O Power  
Ground  
Supply  
Supply  
N/A  
4877 tbl 01  
NOTE:  
1. BW3 and BW4 are not applicable for the IDT71V2579.  
JUNE 2003  
1
©2003ntegratedDeviceTechnology,Inc.  
DSC-4877/08  

与IDT71V2579S85BQI相关器件

型号 品牌 获取价格 描述 数据表
IDT71V2579S85PF IDT

获取价格

128K x 36,256K x 18 3.3V Synchronous SRAMs 2.5V I/O,Flow-Through Outputs Burst Counter,Sin
IDT71V2579S85PF8 IDT

获取价格

Cache SRAM, 256KX18, 8.5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100
IDT71V2579S85PFGI IDT

获取价格

暂无描述
IDT71V2579S85PFI IDT

获取价格

128K x 36,256K x 18 3.3V Synchronous SRAMs 2.5V I/O,Flow-Through Outputs Burst Counter,Sin
IDT71V2579S85PFI8 IDT

获取价格

Cache SRAM, 256KX18, 8.5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100
IDT71V2579SA IDT

获取价格

128K x 36,256K x 18 3.3V Synchronous SRAMs 2.5V I/O,Flow-Through Outputs Burst Counter,Sin
IDT71V2579SA75BG IDT

获取价格

128K x 36,256K x 18 3.3V Synchronous SRAMs 2.5V I/O,Flow-Through Outputs Burst Counter,Sin
IDT71V2579SA75BGI IDT

获取价格

128K x 36,256K x 18 3.3V Synchronous SRAMs 2.5V I/O,Flow-Through Outputs Burst Counter,Sin
IDT71V2579SA75BQ IDT

获取价格

128K x 36,256K x 18 3.3V Synchronous SRAMs 2.5V I/O,Flow-Through Outputs Burst Counter,Sin
IDT71V2579SA75BQI IDT

获取价格

128K x 36,256K x 18 3.3V Synchronous SRAMs 2.5V I/O,Flow-Through Outputs Burst Counter,Sin