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IDT71V2578YSA133BQ PDF预览

IDT71V2578YSA133BQ

更新时间: 2024-11-20 22:08:59
品牌 Logo 应用领域
艾迪悌 - IDT 计数器静态存储器
页数 文件大小 规格书
22页 283K
描述
128K X 36, 256K X 18 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

IDT71V2578YSA133BQ 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:BGA包装说明:FBGA-165
针数:165Reach Compliance Code:not_compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.88最长访问时间:4.2 ns
其他特性:PIPELINED ARCHITECTURE最大时钟频率 (fCLK):133 MHz
I/O 类型:COMMONJESD-30 代码:R-PBGA-B165
JESD-609代码:e0长度:15 mm
内存密度:4718592 bit内存集成电路类型:CACHE SRAM
内存宽度:18湿度敏感等级:3
功能数量:1端子数量:165
字数:262144 words字数代码:256000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:256KX18
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TBGA封装等效代码:BGA165,11X15,40
封装形状:RECTANGULAR封装形式:GRID ARRAY, THIN PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):225
电源:2.5,3.3 V认证状态:Not Qualified
座面最大高度:1.2 mm最大待机电流:0.03 A
最小待机电流:3.14 V子类别:SRAMs
最大压摆率:0.25 mA最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn63Pb37)
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:20
宽度:13 mmBase Number Matches:1

IDT71V2578YSA133BQ 数据手册

 浏览型号IDT71V2578YSA133BQ的Datasheet PDF文件第2页浏览型号IDT71V2578YSA133BQ的Datasheet PDF文件第3页浏览型号IDT71V2578YSA133BQ的Datasheet PDF文件第4页浏览型号IDT71V2578YSA133BQ的Datasheet PDF文件第5页浏览型号IDT71V2578YSA133BQ的Datasheet PDF文件第6页浏览型号IDT71V2578YSA133BQ的Datasheet PDF文件第7页 
128K X 36, 256K X 18  
IDT71V2576S  
IDT71V2578S  
IDT71V2576SA  
IDT71V2578SA  
3.3VSynchronousSRAMs  
2.5V I/O, Pipelined Outputs,  
Burst Counter, Single Cycle Deselect  
Features  
Description  
128K x 36, 256K x 18 memory configurations  
The IDT71V2576/78 are high-speed SRAMs organized as 128K x  
36/256Kx18.TheIDT71V2576/78SRAMscontainwrite,data,address  
andcontrolregisters. InternallogicallowstheSRAMtogenerateaself-  
timedwritebaseduponadecisionwhichcanbeleftuntiltheendofthewrite  
cycle.  
Supports high system speed:  
CommercialandIndustrial:  
– 150MHz 3.8ns clock access time  
– 133MHz 4.2ns clock access time  
LBO input selects interleaved or linear burst mode  
Theburstmodefeatureoffersthehighestlevelofperformancetothe  
Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite systemdesigner,astheIDT71V2576/78canprovidefourcyclesofdata  
enable (BWE), and byte writes (BWx)  
3.3V core power supply  
Power down controlled by ZZ input  
2.5V I/O  
Optional - Boundary Scan JTAG Interface (IEEE 1149.1 operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput  
compliant) datawillbeavailabletotheuseronthenextthreerisingclockedges. The  
Packaged in a JEDEC Standard 100-pin plastic thin quad orderofthesethreeaddressesaredefinedbytheinternalburstcounter  
flatpack(TQFP),119ballgridarray(BGA)and165finepitchball andthe LBO inputpin.  
grid array (fBGA)  
forasingleaddress presentedtotheSRAM. Aninternalburstaddress  
counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe  
accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone  
cycle before it is available on the next rising clock edge. If burst mode  
The IDT71V2576/78 SRAMs utilize IDT’s latest high-performance  
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm  
100-pinthinplasticquadflatpack(TQFP)aswellasa119 ballgridarray  
(BGA) and 165 fine pitch ball grid array (fBGA).  
PinDescriptionSummary  
A0-A17  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Output  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enable  
CE  
CS0, CS1  
OE  
Chip Selects  
Output Enable  
Global Write Enable  
Byte Write Enable  
Individual Byte Write Selects  
Clock  
GW  
BWE  
(1)  
BW1, BW2, BW3, BW4  
CLK  
Burst Address Advance  
Address Status (Cache Controller)  
Address Status (Processor)  
Linear / Interleaved Burst Order  
Test Mode Select  
Test Data Input  
Synchronous  
Synchronous  
Synchronous  
DC  
ADV  
ADSC  
ADSP  
LBO  
TMS  
Synchronous  
Synchronous  
N/A  
TDI  
TCK  
Test Clock  
TDO  
Test Data Output  
Synchronous  
Asynchronous  
Asynchronous  
Synchronous  
N/A  
JTAG Reset (Optional)  
Sleep Mode  
TRST  
ZZ  
I/O0-I/O31, I/OP1-I/OP4  
VDD, VDDQ  
VSS  
Data Input / Output  
Core Power, I/O Power  
Ground  
Supply  
Supply  
N/A  
4876 tbl 01  
NOTE:  
JUNE 2003  
1. BW3 and BW4 are not applicable for the IDT71V2578.  
1
©2003IntegratedDeviceTechnology,Inc.  
DSC-4876/09  

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