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IDT71V2577SA75BGG PDF预览

IDT71V2577SA75BGG

更新时间： 2024-11-06 13:00:19
品牌 Logo 应用领域
艾迪悌 - IDT 计数器静态存储器
页数 文件大小 规格书
22页 291K
描述
Cache SRAM, 128KX36, 7.5ns, CMOS, PBGA119, BGA-119

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中文翻译

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IDT71V2577SA75BGG 技术参数

生命周期：Obsolete零件包装代码：BGA
包装说明：BGA,针数：119
Reach Compliance Code：unknownECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.8
Is Samacsys：NBase Number Matches：1

IDT71V2577SA75BGG 数据手册

 浏览型号IDT71V2577SA75BGG的Datasheet PDF文件第2页浏览型号IDT71V2577SA75BGG的Datasheet PDF文件第3页浏览型号IDT71V2577SA75BGG的Datasheet PDF文件第4页浏览型号IDT71V2577SA75BGG的Datasheet PDF文件第5页浏览型号IDT71V2577SA75BGG的Datasheet PDF文件第6页浏览型号IDT71V2577SA75BGG的Datasheet PDF文件第7页 
IDT71V2577S  
IDT71V2579S  
IDT71V2577SA  
IDT71V2579SA  
128K x 36, 256K x 18  
3.3V Synchronous SRAMs  
2.5V I/O, Flow-Through Outputs  
Burst Counter, Single Cycle Deselect  
Description  
Features  
◆
The IDT71V2577/79 are high-speed SRAMs organized as  
128Kx36/256Kx18.TheIDT71V2577/79SRAMs containwrite,data,  
address andcontrolregisters.Therearenoregisters inthedataoutput  
path (flow-through architecture). Internal logic allows the SRAM to  
generateaself-timedwritebaseduponadecisionwhichcanbeleftuntil  
128K x 36, 256K x 18 memory configurations  
◆
Supports fast access times:  
Commercial:  
– 7.5ns up to 117MHz clock frequency  
CommercialandIndustrial:  
– 8.0ns up to 100MHz clock frequency  
– 8.5ns up to 87MHz clock frequency  
LBO input selects interleaved or linear burst mode  
Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite  
enable (BWE), and byte writes (BWx)  
3.3V core power supply  
Power down controlled by ZZ input  
2.5V I/O  
Optional - Boundary Scan JTAG Interface (IEEE 1149.1  
compliant)  
Packaged in a JEDEC Standard 100-pin plastic thin quad  
flatpack(TQFP),119ballgridarray(BGA)and165finepitchball  
grid array (fBGA)  
theendofthewritecycle.  
Theburstmodefeatureoffersthehighestlevelofperformancetothe  
systemdesigner,astheIDT71V2577/79canprovidefourcyclesofdata  
fora single address presentedtothe SRAM. Aninternalburstaddress  
counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe  
accesssequence.Thefirstcycleofoutputdatawillflow-throughfromthe  
arrayafteraclock-to-dataaccesstimedelayfromtherisingclockedgeof  
the same cycle. If burst mode operation is selected (ADV=LOW), the  
subsequentthreecyclesofoutputdatawillbeavailabletotheuseronthe  
next three rising clock edges. The order of these three addresses are  
definedbytheinternalburstcounterandtheLBOinputpin.  
◆
◆
◆
◆
◆
◆
◆
The IDT71V2577/79 SRAMs utilize IDT’s latest high-performance  
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm  
100-pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray  
(BGA) and a 165 fine pitch ball grid array (fBGA).  
PinDescriptionSummary  
A0-A17  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Synchronous  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
Chip Enable  
CE  
CS0, CS1  
OE  
Chip Selects  
Output Enable  
Global Write Enable  
Byte Write Enable  
Individual Byte Write Selects  
GW  
BWE  
(1)  
BW1, BW2, BW3, BW4  
CLK  
ADV  
ADSC  
ADSP  
LBO  
Clock  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Output  
Input  
Input  
I/O  
N/A  
Synchronous  
Synchronous  
Synchronous  
DC  
Burst Address Advance  
Address Status (Cache Controller)  
Address Status (Processor)  
Linear / Interleaved Burst Order  
Test Mode Select  
Test Data Input  
TMS  
TDI  
Synchronous  
Synchronous  
N/A  
TCK  
TDO  
Test Clock  
Test Data Output  
Synchronous  
Asynchronous  
Asynchronous  
Synchronous  
N/A  
JTAG Reset (Optional)  
Sleep Mode  
TRST  
ZZ  
I/O0-I/O31, I/OP1-I/OP4  
VDD, VDDQ  
VSS  
Data Input / Output  
Core Power, I/O Power  
Ground  
Supply  
Supply  
N/A  
4877 tbl 01  
NOTE:  
1. BW3 and BW4 are not applicable for the IDT71V2579.  
JUNE 2003  
1
©2003ntegratedDeviceTechnology,Inc.  
DSC-4877/08  
1234567...22

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与IDT71V2577SA75BGG相关器件

型号 品牌 获取价格 描述 数据表
IDT71V2577SA75BGI IDT

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 		128K x 36,256K x 18 3.3V Synchronous SRAMs 2.5V I/O,Flow-Through Outputs Burst Counter,Sin
IDT71V2577SA75BQ IDT

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 		128K x 36,256K x 18 3.3V Synchronous SRAMs 2.5V I/O,Flow-Through Outputs Burst Counter,Sin
IDT71V2577SA75BQG IDT

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 		Cache SRAM, 128KX36, 7.5ns, CMOS, PBGA165, FBGA-165
IDT71V2577SA75BQI IDT

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 		128K x 36,256K x 18 3.3V Synchronous SRAMs 2.5V I/O,Flow-Through Outputs Burst Counter,Sin
IDT71V2577SA75PF IDT

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 		128K x 36,256K x 18 3.3V Synchronous SRAMs 2.5V I/O,Flow-Through Outputs Burst Counter,Sin
IDT71V2577SA75PFI IDT

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 		128K x 36,256K x 18 3.3V Synchronous SRAMs 2.5V I/O,Flow-Through Outputs Burst Counter,Sin
IDT71V2577SA80BG IDT

获取价格

 		128K x 36,256K x 18 3.3V Synchronous SRAMs 2.5V I/O,Flow-Through Outputs Burst Counter,Sin
IDT71V2577SA80BGGI IDT

获取价格

 		Cache SRAM, 128KX36, 8ns, CMOS, PBGA119, BGA-119
IDT71V2577SA80BGI IDT

获取价格

 		128K x 36,256K x 18 3.3V Synchronous SRAMs 2.5V I/O,Flow-Through Outputs Burst Counter,Sin
IDT71V2577SA80BQ IDT

获取价格

 		128K x 36,256K x 18 3.3V Synchronous SRAMs 2.5V I/O,Flow-Through Outputs Burst Counter,Sin

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